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Undetectable PMU Timing-Attack on Linear State-Estimation by UsingRank-1 Approximation
EPFL.
EPFL.
KTH, School of Electrical Engineering (EES), Network and Systems engineering.
EPFL.
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2016 (English)In: IEEE Transactions on Smart Grid, ISSN 1949-3053, E-ISSN 1949-3061Article in journal (Refereed) Published
Abstract [en]

Smart-grid applications based on synchrophasor measurements have recently been shown to be vulnerable to timing attacks. A fundamental question is whether timing attacks could remain undetected by bad-data detection algorithms used in conjunction with state-of-the-art situational-awareness state estimators. In this paper, we analyze the detectability of timing attacks on linear state-estimation. We show that it is possible to forge delay attacks that are undetectable. We give a closed form for an undetectable attack; it imposes two phase offsets to two or more synchrophasor-based measurement units that can be translated to synchrophasors’ time delays. We also propose different methods for combining two-delays attacks to produce a larger impact. We simulate the attacks on a benchmark powertransmission grid, we show that they are successful and can lead to physical grid damage. To prove undetectability, we use classic bad-data detection techniques such as the largest normalized residual and the 2-test.

Place, publisher, year, edition, pages
IEEE Press, 2016.
Keyword [en]
Time Synchronization Attack, False Data Injection, Phasor Measurement Units, Linear State Estimation
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-215255DOI: 10.1109/TSG.2016.2634124OAI: oai:DiVA.org:kth-215255DiVA, id: diva2:1147271
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Note

QC 20171107

Available from: 2017-10-05 Created: 2017-10-05 Last updated: 2017-11-07Bibliographically approved

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