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Integrated Logic Synthesis Using Simulated Annealing
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
2007 (English)Doctoral thesis, monograph (Other scientific)
Abstract [en]

A conventional logic synthesis flow is composed of three separate phases: technologyindependent optimization, technology mapping, and technology dependentoptimization. A fundamental problem with such a three-phased approach is thatthe global logic structure is decided during the first phase without any knowledge ofthe actual technology parameters considered during later phases. Although technologydependent optimization algorithms perform some limited logic restructuring,they cannot recover from fundamental mistakes made during the first phase, whichoften results in non-satisfiable solutions.We present a global optimization approach combining technology independentoptimization steps with technology dependent objectives in an annealing-basedframework. We prove that, for the presented move set and selection distribution, detailedbalance is satisfied and thus the annealing process asymptotically convergesto an optimal solution. Furthermore, we show that the presented approach cansmoothly trade-off complex, multiple-dimensional objective functions and achievecompetitive results. The combination of technology independent and technologydependent objectives is handled through dynamic weighting. Dynamic weightingreflects the sensitivity of the local graph structures with respect to the actual technologyparameters such as gate sizes, delays, and power levels. The results showthat, on average, the presented advanced annealing approach can improve the areaand delay of circuits optimized using the Boolean optimization technique providedby SIS with 11.2% and 32.5% respectively.Furthermore, we demonstrate how the developed logic synthesis framework canbe applied to two emerging technologies, chemically assembled nanotechnology andmolecule cascades. New technologies are emerging because a number of physicaland economic factors threaten the continued scaling of CMOS devices. Alternativesto silicon VLSI have been proposed, including techniques based on molecularelectronics, quantum mechanics, and biological processes. We are hoping that ourresearch in how to apply our developed logic synthesis framework to two of theemerging technologies might provide useful information for other designers movingin this direction.

Place, publisher, year, edition, pages
Stockholm: KTH , 2007. , xii, 157 p.
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 07:01
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-4257ISBN: 978-91-7178-516-9ISBN: 91-7178-516-7OAI: diva2:11493
Public defence
2007-01-26, Sal E, KTH-Forum, Isafjordsgatan 39, Kista, 09:00
QC 20100709Available from: 2006-12-29 Created: 2006-12-29 Last updated: 2010-09-16Bibliographically approved

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