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Distributed Two-stage Network Topology Processor for HVDC Grid Operation
KTH, School of Electrical Engineering (EES), Electric Power and Energy Systems.ORCID iD: 0000-0003-3946-7655
KTH, School of Electrical Engineering (EES), Electric Power and Energy Systems.
KTH, School of Electrical Engineering (EES), Electric Power and Energy Systems.ORCID iD: 0000-0002-6330-3055
KTH, School of Electrical Engineering (EES), Electric Power and Energy Systems.ORCID iD: 0000-0003-3014-5609
2017 (English)In: 2017 IEEE MANCHESTER POWERTECH, IEEE , 2017Conference paper (Refereed)
Abstract [en]

This paper presents the results of an analysis of distributed two-stage coordination of network topology processor for HVDC grids. In the first stage of the two-stage processor, the substation topology is analyzed locally using an automated graphbased algorithm. Thereafter, a distributed algorithm is proposed to used the neighboring information to realize the grid connectivity. For distributed islanding detection, the connectivity problem is formulated as a set of linear equations and solved iteratively using successive-over-relaxation method. The performance of the proposed methods versus conventional one-stage method has been tested in an islanding scenario for a 5-terminal HVDC grid.

Place, publisher, year, edition, pages
IEEE , 2017.
Keyword [en]
distributed coordination, HVDC grid, topology processor
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-215849ISI: 000411142500054ISBN: 978-1-5090-4237-1 OAI: oai:DiVA.org:kth-215849DiVA: diva2:1149775
Conference
IEEE Manchester PowerTech, JUN 18-22, 2017, Manchester, ENGLAND
Note

QC 20171017

Available from: 2017-10-17 Created: 2017-10-17 Last updated: 2017-10-17Bibliographically approved

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Babazadeh, DavoodYiming, WuNordström, Lars

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