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Low-latency hardware architecture for cipher-based message authentication code
KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
2017 (English)In: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Institute of Electrical and Electronics Engineers (IEEE), 2017, article id 8050840Conference paper (Refereed)
Abstract [en]

Cipher-based message authentication code, CMAC, is a NIST approved standard for checking message integrity and authentication. This work presents a low-latency AES architecture for CMAC. The architecture uses intensive parallel processing per round and takes advantage of the BRAM present in modern FPGA. Experimental results show that for typical IoT application, the proposed architecture has a latency of 10 clock cycles, consumes 1355 slices, 2 BRAMs and achieves a throughput of 3.8Gbps.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2017. article id 8050840
Series
Proceedings - IEEE International Symposium on Circuits and Systems, ISSN 0271-4310
National Category
Other Engineering and Technologies
Identifiers
URN: urn:nbn:se:kth:diva-217487DOI: 10.1109/ISCAS.2017.8050840Scopus ID: 2-s2.0-85032678248ISBN: 9781467368520 OAI: oai:DiVA.org:kth-217487DiVA, id: diva2:1156502
Conference
50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, United States, 28 May 2017 through 31 May 2017
Note

QC 20171113

Available from: 2017-11-13 Created: 2017-11-13 Last updated: 2017-11-13Bibliographically approved

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  • apa
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  • nn-NB
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  • Other locale
More languages
Output format
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  • asciidoc
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