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Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip
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2017 (English)In: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Institute of Electrical and Electronics Engineers (IEEE), 2017, article id 8050828Conference paper, Published paper (Refereed)
Abstract [en]

To achieve high reliability in on-chip networks, frequent runs of Built-in Self-Test allow the detection of and recovery from faults before they affect packets and the system functionality. However, to test routers, wrappers isolate cores from the network which leads to execution blocking and performance loss. In this paper, we propose a design-for-test reconfigurable router with two alternative bypassing channels. The router architecture allows maintaining the connection between cores and the network during the testing procedure by utilizing the bypassing channels. With the help of an adaptive routing algorithm and a testing strategy, networks can be fully tested at a high testing frequency with <15% increase of execution time.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2017. article id 8050828
Series
Proceedings - IEEE International Symposium on Circuits and Systems, ISSN 0271-4310
National Category
Other Engineering and Technologies
Identifiers
URN: urn:nbn:se:kth:diva-217486DOI: 10.1109/ISCAS.2017.8050828ISI: 000439261800057Scopus ID: 2-s2.0-85032686628ISBN: 9781467368520 OAI: oai:DiVA.org:kth-217486DiVA, id: diva2:1156528
Conference
50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, United States, 28 May 2017 through 31 May 2017
Note

QC 20171113

Available from: 2017-11-13 Created: 2017-11-13 Last updated: 2018-08-07Bibliographically approved

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  • Other locale
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