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A 40GHz PLL with -92.5dBc/Hz in-band phase noise and 104fs-RMS-jitter
KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
2017 (English)In: Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, Institute of Electrical and Electronics Engineers Inc. , 2017, 31-32 p.Conference paper (Refereed)
Abstract [en]

This paper demonstrates a fully integrated low phase noise PLL at 40GHz, implemented in a 0.25-μm SiGe:C BiCMOS technology. An in-band phase noise improvement of 1.4dB to 3.2dB is measured across the locking range using the proposed double-gain PFD. The PLL achieves an in-band phase noise <-92.5dBc/Hz and an integrated RMS jitter of 104fs, a 25% improvement over conventional PFD. The reference spurs are <-73dBc across the whole locking range.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc. , 2017. 31-32 p.
Keyword [en]
Ka-band, low phase noise, PFD, PLL, Jitter, Locks (fasteners), Phase locked loops, Radio waves, Semiconducting silicon, Fully integrated, In-band phase noise, Ka band, Locking range, Reference spur, RMS jitter, SiGe:C BiCMOS technology, Phase noise
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-216293DOI: 10.1109/RFIC.2017.7969009Scopus ID: 2-s2.0-85026850736ISBN: 9781509046263 OAI: oai:DiVA.org:kth-216293DiVA: diva2:1164552
Conference
2017 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2017, 4 June 2017 through 6 June 2017
Note

QC 20171211

Available from: 2017-12-11 Created: 2017-12-11 Last updated: 2017-12-11Bibliographically approved

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Ivanisevic, Nikola

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  • nn-NO
  • nn-NB
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  • Other locale
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