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Synchoricity and NOCs could make Billion Gate custom hardware centric SOCs affordable
KTH, School of Information and Communication Technology (ICT), Electronics.ORCID iD: 0000-0003-0565-9376
KTH, School of Information and Communication Technology (ICT), Electronics.
2017 (English)In: 2017 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017, Association for Computing Machinery (ACM), 2017, article id 8Conference paper (Refereed)
Abstract [en]

In this paper, we present a novel synchoros VLSI design scheme that discretizes space uniformly. Synchoros derives from the Greek word chóros for space. We propose raising the physical design abstraction to register transfer level by using coarse grain reconfigurable building blocks called SiLago blocks. SiLago blocks are hardened, synchoros and are used to create arbitrarily complex VLSI design instances by abutting them and not requiring any further logic and physical syntheses. SiLago blocks are interconnected by two levels of NOCs, regional and global. By configuring the SiLago blocks and the two levels of NOCs, it is possible to create implementation alternatives whose cost metrics can be evaluated with agility and post layout accuracy. This framework, called the SiLago framework includes a synthesis based design flow that allows end to end automation of multi-million gate functionality modeled as SDF in Simulink to be transformed into timing and DRC clean physical design in minutes, while exploring 100s of solutions. We benchmark the synthesis efficiency, and silicon and computational efficiencies against the conventional standard cell based tooling to show two orders improvement in accuracy and three orders improvement in synthesis while eliminating the need to verify at lower abstractions like RTL. The proposed solution is being extended to deal with system-level non-compile time functionalities. We also present arguments on how synchoricity could also contribute to eliminating the engineering cost of designing masks to lower the manufacturing cost.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2017. article id 8
Keywords [en]
ASICs, Coarse Grain Reconfiguration, ESL, High-level Synthesis, NOCs, SOCs, Synchoricity, VLSI Design
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:kth:diva-219649DOI: 10.1145/3130218.3132339Scopus ID: 2-s2.0-85035780779ISBN: 9781450349840 OAI: oai:DiVA.org:kth-219649DiVA, id: diva2:1165330
Conference
11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017, Seoul, South Korea, 19 October 2017 through 20 October 2017
Funder
VINNOVA
Note

QC 20171213

Available from: 2017-12-13 Created: 2017-12-13 Last updated: 2017-12-13Bibliographically approved

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Hemani, Ahmed

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