Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Towards performance-oriented pattern-based refinement of synchronous models onto NoC communication
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0003-0061-3475
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0003-4859-3100
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2006 (English)In: DSD 2006: 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, Proceedings / [ed] Muthukumar V, 2006, 37-44 p.Conference paper, Published paper (Refereed)
Abstract [en]

We present a performance-oriented refinement approach that refines a perfectly synchronous communication model onto Network-on-Chip (NoC) communication. We first identify four basic forms of NoC process interaction patterns at the process level, namely, producer-consumer, peers, client-server and multicast. We propose a three-step top-down refinement method: channel refinement, protocol refinement and channel mapping. For the producer-consumer pattern, we describe it in detail. In channel refinement, we deal with interfacing multiple clock domains and use a stochastic process to model channel delay and jitter In protocol refinement, we show how to refine communication towards application requirements such as reliability and throughput. In channel mapping, we discuss channel convergence and channel merge arising from channel overlapping. All the refinements have been conducted and validated as an integral design phase towards implementation in ForSyDe, a formal system-level design methodology based on a synchronous model of computation.

Place, publisher, year, edition, pages
2006. 37-44 p.
National Category
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-6844DOI: 10.1109/DSD.2006.89ISI: 000242376400006Scopus ID: 2-s2.0-34547995122ISBN: 0-7695-2609-8 (print)OAI: oai:DiVA.org:kth-6844DiVA: diva2:11665
Conference
9th EUROMICRO Conference on Digital System Design - Architectures, Methods and Tools Cavtat, CROATIA, AUG 30-SEP 01, 2006
Note

QC 20110207

Available from: 2007-02-28 Created: 2007-02-28 Last updated: 2016-08-22Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Authority records BETA

Lu, ZhonghaiSander, Ingo

Search in DiVA

By author/editor
Lu, ZhonghaiSander, IngoJantsch, Axel
By organisation
Electronic, Computer and Software Systems, ECS
Computer Science

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 39 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf