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Design and Analysis of On-Chip Communication for Network-on-Chip Platforms
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0003-0061-3475
2007 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

Due to the interplay between increasing chip capacity and complex applications, System-on-Chip (SoC) development is confronted by severe challenges, such as managing deep submicron effects, scaling communication architectures and bridging the productivity gap. Network-on-Chip (NoC) has been a rapidly developed concept in recent years to tackle the crisis with focus on network-based communication. NoC problems spread in the whole SoC spectrum ranging from specification, design, implementation to validation, from design methodology to tool support. In the thesis, we formulate and address problems in three key NoC areas, namely, on-chip network architectures, NoC network performance analysis, and NoC communication refinement.

Quality and cost are major constraints for micro-electronic products, particularly, in high-volume application domains. We have developed a number of techniques to facilitate the design of systems with low area, high and predictable performance. From flit admission and ejection perspective, we investigate the area optimization for a classical wormhole architecture. The proposals are simple but effective. Not only offering unicast services, on-chip networks should also provide effective support for multicast. We suggest a connection-oriented multicasting protocol which can dynamically establish multicast groups with quality-of-service awareness. Based on the concept of a logical network, we develop theorems to guide the construction of contention-free virtual circuits, and employ a back-tracking algorithm to systematically search for feasible solutions.

Network performance analysis plays a central role in the design of NoC communication architectures. Within a layered NoC simulation framework, we develop and integrate traffic generation methods in order to simulate network performance and evaluate network architectures. Using these methods, traffic patterns may be adjusted with locality parameters and be configured per pair of tasks. We propose also an algorithm-based analysis method to estimate whether a wormhole-switched network can satisfy the timing constraints of real-time messages. This method is built on traffic assumptions and based on a contention tree model that captures direct and indirect network contentions and concurrent link usage.

In addition to NoC platform design, application design targeting such a platform is an open issue. Following the trends in SoC design, we use an abstract and formal specification as a starting point in our design flow. Based on the synchronous model of computation, we propose a top-down communication refinement approach. This approach decouples the tight global synchronization into process local synchronization, and utilizes synchronizers to achieve process synchronization consistency during refinement. Meanwhile, protocol refinement can be incorporated to satisfy design constraints such as reliability and throughput.

The thesis summarizes the major research results on the three topics.

Place, publisher, year, edition, pages
Stockholm: KTH , 2007. , xvi, 109 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 2007:02
Keyword [en]
On-Chip Communication, Network-on-Chip, System-on-Chip
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-4290ISBN: 978-91-7178-580-0 (print)OAI: oai:DiVA.org:kth-4290DiVA: diva2:11666
Public defence
2007-03-15, D, KTH Forum, Isafördsgatan 39, Kista, 13:00 (English)
Opponent
Supervisors
Note
QC 20100525Available from: 2007-02-28 Created: 2007-02-28 Last updated: 2010-08-06Bibliographically approved
List of papers
1. Flit admission in on-chip wormhole-switched networks with virtual channels
Open this publication in new window or tab >>Flit admission in on-chip wormhole-switched networks with virtual channels
2004 (English)In: 2004 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS, IEEE conference proceedings, 2004, 21-24 p.Conference paper, Published paper (Refereed)
Abstract [en]

Flit-admission solutions for wormhole switches must minimize the complexity of the switches in order to achieve cheap implementations. We propose to couple flit-admission buffers with physical channels so that flits from a flit-admission buffer are dedicated to a physical channel. By the coupling strategy, for input-queuing wormhole lane switches, the complexity of the crossbars can be simplified from 2p x p to (p + 1) x p, where p is the number of physical channels; for output-queuing wormhole lane switches, the additional complexity is also minimal. We evaluate the flit-admission solutions derived from the coupling with uniformly distributed random traffic in a 2D mesh network. Experimental results show that these solutions exhibit good performance in terms of latency and throughput.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2004
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-13036 (URN)000227185900005 ()2-s2.0-21244466371 (Scopus ID)
Conference
International Symposium on System-on-Chip, Tampere, Finland, November 2004.
Note

QC 20100524. QC 20160212

Available from: 2010-05-24 Created: 2010-05-24 Last updated: 2016-02-12Bibliographically approved
2. Flit ejection in on-chip wormhole-switched networks with virtual channels
Open this publication in new window or tab >>Flit ejection in on-chip wormhole-switched networks with virtual channels
2004 (English)In: 22ND NORCHIP CONFERENCE, PROCEEDINGS, IEEE conference proceedings, 2004, 273-276 p.Conference paper, Published paper (Refereed)
Abstract [en]

An ideal it-ejection model is typically assumed in the literature for wormhole switches with virtual channels. With such a model, its are ejected from the network immediately upon reaching their destinations. This achieves optimal performance but is very costly. The required number of sink queues of a switch for absorbing its is p center dot v, where p is the number of physical channels (PCs) of the switch; v the number of lanes per PC To achieve cheap silicon implementations, it-ejection solutions must be cost-effective. We present a novel it-ejection model and a variant of it where the required number of sink queues of a switch is p, i.e., independent of v. We evaluate the it-ejection models with uniformly distributed random traf c in a 2D mesh network. Experimental results show that they exhibit good performance in latency and throughput.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2004
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-13037 (URN)10.1109/NORCHP.2004.1423876 (DOI)000227801500068 ()2-s2.0-21244435987 (Scopus ID)
Conference
IEEE NorChip Conference, Oslo, Norway, November 2004.
Note

QC 20100524. QC 20160212

Available from: 2010-05-24 Created: 2010-05-24 Last updated: 2016-02-12Bibliographically approved
3. Connection-oriented multicasting in wormhole-switched networks on chip
Open this publication in new window or tab >>Connection-oriented multicasting in wormhole-switched networks on chip
2006 (English)In: IEEE Computer Society Annual Symposium on VLSI, Proceedings - EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2006, 205-210 p.Conference paper, Published paper (Refereed)
Abstract [en]

Network-on-Chip (NoC) proposes networks to replace buses as a scalable global communication interconnect for future SoC designs. However, a bus is very efficient in broadcasting. As the system size scales up to explore the chip capacity, broadcasting in NoCs must be efficiently supported. This paper presents a novel multicast scheme in wormhole-switched NoCs. By this scheme, a multicast procedure consists of establishment, communication and release phase. A multicast group can request to reserve virtual channels during establishment and has priority on arbitration of link bandwidth. This multicasting method has been effectively implemented in a mesh network with dead-lock freedom. Our experiments show that the multicast technique improves throughput, and does not exhibit significant impact on unicast performance in a network with mixed unicast and multicast traffic if the network is not saturated.

Keyword
Communication channels (information theory); Interconnection networks; Microprocessor chips; Switching networks; Telecommunication traffic; Throughput; Chip capacity; Global communication interconnect; Multicast traffic; Virtual channels; Multicasting
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-13057 (URN)10.1109/ISVLSI.2006.31 (DOI)000237225200032 ()2-s2.0-33749348991 (Scopus ID)
Conference
ISVLSI'2006
Note

QC 20100525. QC 20160212

Available from: 2010-05-25 Created: 2010-05-25 Last updated: 2016-02-12Bibliographically approved
4. TDM virtual-circuit configuration for network-on-chip
Open this publication in new window or tab >>TDM virtual-circuit configuration for network-on-chip
2008 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 16, no 8, 1021-1034 p.Article in journal (Refereed) Published
Abstract [en]

In network-on-chip (NoC), time-division-multiplexing (TDM) virtual circuits (VCs) have been proposed to satisfy the quality-of-service requirements of applications. TDM VC is a connection-oriented communication service by which two or more connections take turns to share buffers and link bandwidth using dedicated time slots. In the paper, we first give a formulation of the multinode VC configuration problem for arbitrary NoC topologies. A multinode VC allows multiple source and destination nodes on it. Then we address the two problems of path selection and slot allocation for TDM VC configuration. For the path selection, we use a backtracking algorithm to explore the path diversity, constructively searching the solution space. In the slot allocation phase, overlapped VCs must be configured such that no conflict occurs and their bandwidth requirements are satisfied. We define the concept of a logical network (LN) as an infinite set of associated (time slot, buffer) pairs with respect to a buffer on a given VC. Based on this concept, we develop and prove theorems that constitute sufficient and necessary conditions to establish conflict-free VCs. They are applicable for networks where all nodes operate with the same clock frequency but allowing different phases. Using these theorems, slot allocation for VCs is a procedure of assigning VCs to different LNs. TDM VC configuration can thus be predictable and correct-by-construction. Our experiments on synthetic and real applications validate the effectiveness and efficiency of our approach.

Keyword
Logical network, network-on-chip (NoC), quality of service (QoS), time division multiplexing (TDM), virtual circuit
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-13058 (URN)10.1109/TVLSI.2008.2000673 (DOI)000257987400008 ()2-s2.0-48349101315 (Scopus ID)
Note
QC 20100525Available from: 2010-05-25 Created: 2010-05-25 Last updated: 2017-12-12Bibliographically approved
5. Traffic configuration for evaluating networks on chips
Open this publication in new window or tab >>Traffic configuration for evaluating networks on chips
2005 (English)In: Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings, IEEE Computer Society, 2005, 535-540 p.Conference paper, Published paper (Refereed)
Abstract [en]

Network-on-Chip (NoC) provides a network as a global communication platform for future SoC designs. Evaluating network architectures requires both synthetic workloads and application-oriented traffic. We present our traffic configuration methods that can be used to configure uniform and locality traffic as synthetic workloads, and to configure channel-based traffic for specific application(s). We also illustrate the significance of applying these methods to configure traffic for network evaluation and system simulation. These traffic configuration methods have been integrated into our Nostrum NoC simulation environment.

Place, publisher, year, edition, pages
IEEE Computer Society, 2005
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-13038 (URN)000231591800102 ()2-s2.0-33748913346 (Scopus ID)0-7695-2403-6 (ISBN)
Conference
5th International Workshop on System-on- Chip for Real-time Applications, Alberta, Canada, July 2005
Note

QC 20100524. QC 20160209

Available from: 2010-05-24 Created: 2010-05-24 Last updated: 2016-02-09Bibliographically approved
6. Connection-oriented multicasting in wormhole-switched networks on chip
Open this publication in new window or tab >>Connection-oriented multicasting in wormhole-switched networks on chip
2006 (English)In: Proceedings of the 16th ACM Great Lakes symposium on VLSI, Association for Computing Machinery (ACM), 2006, 296-301 p.Conference paper, Published paper (Refereed)
Abstract [en]

Deflection routing is being proposed for networks on chips since it is simple and adaptive. A deflection switch can be much smaller and faster than a wormhole or virtual cut-through switch. A deflection-routed network has three orthogonal characteristics: topology, routing algorithm and deflection policy. In this paper we evaluate deflection networks with different topologies such as mesh, torus and Manhattan Street Network, different routing algorithms such as random, dimension XY, delta XY and minimum deflection, as well as different deflection policies such as non-priority, weighted priority and straight-through policies. Our results suggest that the performance of a deflection network is more sensitive to its topology than the other two parameters. It is less sensitive to its routing algorithm, but a routing algorithm should be minimal. A priority-based deflection policy that uses global and history-related criterion can achieve both better average-case and worst-case performance than a non-priority or priority policy that uses local and stateless criterion. These findings are important since they can guide designers to make right decisions on the deflection network architecture, for instance, selecting a routing algorithm or deflection policy which has potentially low cost and high speed for hardware implementation.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2006
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-6841 (URN)2-s2.0-33750928209 (Scopus ID)
Conference
Great Lakes Symposium on VLSI
Note

QC 20100525. QC 20160212.

Available from: 2007-02-28 Created: 2007-02-28 Last updated: 2016-02-12Bibliographically approved

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