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Extending Real-Time Analysis for Wormhole NoCs
KTH, School of Information and Communication Technology (ICT), Electronics.ORCID iD: 0000-0003-0061-3475
2017 (English)In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 66, no 9, p. 1532-1546, article id 7884964Article in journal (Refereed) Published
Abstract [en]

The delay upper-bound analysis problem is of fundamental importance to real-Time applications in Network-on-Chips (NoCs). In the paper, we revisit two state-of-The-Art analysis models for real-Time communication in wormhole NoCs with priority-based preemptive arbitration and show that the models only support specific router architectures with large buffer sizes. We then propose an extended analysis model to estimate delay upper-bounds for all router architectures and buffer sizes by identifying and analyzing the differences between upstream and downstream indirect interferences according to the relative positions of traffic flows and taking the buffer influence into consideration. Simulated evaluations show that our model supports one more router architecture and applies to small buffer sizes compared to the previous models.

Place, publisher, year, edition, pages
IEEE Computer Society , 2017. Vol. 66, no 9, p. 1532-1546, article id 7884964
Keywords [en]
delay, real-Time communication, Wormhole NoC, Computer architecture, Network architecture, Routers, Extended analysis, Real time analysis, Real-time application, Relative positions, Router architecture, Upper bound analysis, Network-on-chip
National Category
Computer and Information Sciences
Identifiers
URN: urn:nbn:se:kth:diva-216210DOI: 10.1109/TC.2017.2686391ISI: 000407449400006Scopus ID: 2-s2.0-85029510717OAI: oai:DiVA.org:kth-216210DiVA, id: diva2:1167103
Note

QC 20171218

Available from: 2017-12-18 Created: 2017-12-18 Last updated: 2018-01-13Bibliographically approved

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Lu, Zhonghai

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