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Probabilistic verification based on function hashing
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.ORCID iD: 0000-0001-7382-9408
(English)Manuscript (Other academic)
National Category
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-6855OAI: oai:DiVA.org:kth-6855DiVA: diva2:11679
Note
QC 20110215Available from: 2007-03-01 Created: 2007-03-01 Last updated: 2011-02-15Bibliographically approved
In thesis
1. Graph dominators in logic synthesis and verification
Open this publication in new window or tab >>Graph dominators in logic synthesis and verification
2004 (English)Licentiate thesis, comprehensive summary (Other scientific)
Abstract [en]

This work focuses on the usage of dominators in circuit graphs in order to reduce the complexity of synthesis and verification tasks. One of the contributions of this thesis is a new algorithm for computing multiple-vertex dominators in circuit graphs. Previous algorithms, based on single-vertex dominators suffer from their rare appearance in many circuits. The presented approach searches efficiently for multiple-vertex dominators in circuit graphs. It finds dominator relations, where algorithms for computing single-vertex dominators fail. Another contribution of this thesis is the application of dominators for combinational equivalence checking based on the arithmetic transform. Previous algorithms rely on representations providing an explicit or implicit disjoint function cover, which is usually excessive in memory requirements. The new algorithm allows a partitioned evaluation of the arithmetic transform directly on the circuit graph using dominator relations. The results show that the algorithm brings significant improvements in memory consumption for many benchmarks. Proper cuts are used in many areas of VLSI. They provide cut points, where a given problem can be split into two disjoint sub-problems. The algorithm proposed in this thesis efficiently detects proper cuts in a circuit graph and is based on a novel concept of a reduced dominator tree. The runtime of the algorithm is less than 0.4 seconds for the largest benchmark circuit. The final contribution of this thesis is the application of the proper cut algorithm as a structural method to decompose a Boolean function, represented by a circuit graph. In combination with a functional approach, it outperforms previous methods, which rely on functional decomposition only.

Series
Trita-IMIT. LECS, ISSN 1651-4076 ; 2004:04
Keyword
formal verification, logic synthesis, dominators, equivalence checking, decomposition
National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-4293 (URN)
Available from: 2007-03-01 Created: 2007-03-01 Last updated: 2012-03-20

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Dubrova, Elena

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