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A polynomial-time algorithm for computing bound sets
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0001-7382-9408
2006 (English)In: IEE Proceedings - Circuits Devices and Systems, ISSN 1350-2409, E-ISSN 1359-7000, Vol. 153, no 2, 179-184 p.Article in journal (Refereed) Published
Abstract [en]

An algorithm for computing bound sets of a Boolean function on its circuit representation is presented. The identification of bound sets is useful for many applications in logic synthesis, formal verification and testing. The presented algorithm computes bound sets by analysing dominator relations of the circuit. It has O(e . log n) worst-case complexity, where e is the number of edges and n is the number of vertices of the circuit graph. The experimental results show that the algorithm is efficient for large functions and allows computing bound sets for cases that were not possible to handle with previous methods.

Place, publisher, year, edition, pages
2006. Vol. 153, no 2, 179-184 p.
Keyword [en]
Algorithms, Computational complexity, Formal logic, Graph theory, Networks (circuits), Set theory
National Category
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-6856DOI: 10.1049/ip-cds:20041261ISI: 000237555600015Scopus ID: 2-s2.0-33645000726OAI: oai:DiVA.org:kth-6856DiVA: diva2:11680
Note

QC 20100927. Uppdaterad från Manuskript till Artikel (20100927).

QC 20150727

Available from: 2007-03-01 Created: 2007-03-01 Last updated: 2015-07-27Bibliographically approved
In thesis
1. Graph dominators in logic synthesis and verification
Open this publication in new window or tab >>Graph dominators in logic synthesis and verification
2004 (English)Licentiate thesis, comprehensive summary (Other scientific)
Abstract [en]

This work focuses on the usage of dominators in circuit graphs in order to reduce the complexity of synthesis and verification tasks. One of the contributions of this thesis is a new algorithm for computing multiple-vertex dominators in circuit graphs. Previous algorithms, based on single-vertex dominators suffer from their rare appearance in many circuits. The presented approach searches efficiently for multiple-vertex dominators in circuit graphs. It finds dominator relations, where algorithms for computing single-vertex dominators fail. Another contribution of this thesis is the application of dominators for combinational equivalence checking based on the arithmetic transform. Previous algorithms rely on representations providing an explicit or implicit disjoint function cover, which is usually excessive in memory requirements. The new algorithm allows a partitioned evaluation of the arithmetic transform directly on the circuit graph using dominator relations. The results show that the algorithm brings significant improvements in memory consumption for many benchmarks. Proper cuts are used in many areas of VLSI. They provide cut points, where a given problem can be split into two disjoint sub-problems. The algorithm proposed in this thesis efficiently detects proper cuts in a circuit graph and is based on a novel concept of a reduced dominator tree. The runtime of the algorithm is less than 0.4 seconds for the largest benchmark circuit. The final contribution of this thesis is the application of the proper cut algorithm as a structural method to decompose a Boolean function, represented by a circuit graph. In combination with a functional approach, it outperforms previous methods, which rely on functional decomposition only.

Series
Trita-IMIT. LECS, ISSN 1651-4076 ; 2004:04
Keyword
formal verification, logic synthesis, dominators, equivalence checking, decomposition
National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-4293 (URN)
Available from: 2007-03-01 Created: 2007-03-01 Last updated: 2012-03-20

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Dubrova, Elena

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