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Disjoint-support boolean decomposition combining functional and structural methods
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0001-7382-9408
2004 (English)In: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 2004, 2004, 597-599 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents an algorithm for disjoint-support decomposition of Boolean functions which combines functional and structural approaches. First, a set of proper cut points is identified in the circuit by using dominator relations (structural method). Then, the circuit is partitioned along these cut points and a BDD-based decomposition is applied to the resulting smaller functions (functional method). Previous work on Boolean decomposition used only single methods and did not integrate a combined strategy. The experimental results show that the presented technique is more robust than a pure BDD-based approach and produces better-quality decompositions.

Place, publisher, year, edition, pages
2004. 597-599 p.
National Category
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-6858ISI: 000221356700133Scopus ID: 2-s2.0-2442599137OAI: oai:DiVA.org:kth-6858DiVA: diva2:11682
Conference
Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004; Yokohama; Japan; 27 January 2004 through 30 January 2004;
Note

Uppdaterad från manuskript till konferensbidrag: 20100909 QC 20100909 QC 20150710

Available from: 2007-03-01 Created: 2007-03-01 Last updated: 2015-07-10Bibliographically approved
In thesis
1. Graph dominators in logic synthesis and verification
Open this publication in new window or tab >>Graph dominators in logic synthesis and verification
2004 (English)Licentiate thesis, comprehensive summary (Other scientific)
Abstract [en]

This work focuses on the usage of dominators in circuit graphs in order to reduce the complexity of synthesis and verification tasks. One of the contributions of this thesis is a new algorithm for computing multiple-vertex dominators in circuit graphs. Previous algorithms, based on single-vertex dominators suffer from their rare appearance in many circuits. The presented approach searches efficiently for multiple-vertex dominators in circuit graphs. It finds dominator relations, where algorithms for computing single-vertex dominators fail. Another contribution of this thesis is the application of dominators for combinational equivalence checking based on the arithmetic transform. Previous algorithms rely on representations providing an explicit or implicit disjoint function cover, which is usually excessive in memory requirements. The new algorithm allows a partitioned evaluation of the arithmetic transform directly on the circuit graph using dominator relations. The results show that the algorithm brings significant improvements in memory consumption for many benchmarks. Proper cuts are used in many areas of VLSI. They provide cut points, where a given problem can be split into two disjoint sub-problems. The algorithm proposed in this thesis efficiently detects proper cuts in a circuit graph and is based on a novel concept of a reduced dominator tree. The runtime of the algorithm is less than 0.4 seconds for the largest benchmark circuit. The final contribution of this thesis is the application of the proper cut algorithm as a structural method to decompose a Boolean function, represented by a circuit graph. In combination with a functional approach, it outperforms previous methods, which rely on functional decomposition only.

Series
Trita-IMIT. LECS, ISSN 1651-4076 ; 2004:04
Keyword
formal verification, logic synthesis, dominators, equivalence checking, decomposition
National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-4293 (URN)
Available from: 2007-03-01 Created: 2007-03-01 Last updated: 2012-03-20
2. Advances in Functional Decomposition: Theory and Applications
Open this publication in new window or tab >>Advances in Functional Decomposition: Theory and Applications
2006 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Functional decomposition aims at finding efficient representations for Boolean functions. It is used in many applications, including multi-level logic synthesis, formal verification, and testing.

This dissertation presents novel heuristic algorithms for functional decomposition. These algorithms take advantage of suitable representations of the Boolean functions in order to be efficient.

The first two algorithms compute simple-disjoint and disjoint-support decompositions. They are based on representing the target function by a Reduced Ordered Binary Decision Diagram (BDD). Unlike other BDD-based algorithms, the presented ones can deal with larger target functions and produce more decompositions without requiring expensive manipulations of the representation, particularly BDD reordering.

The third algorithm also finds disjoint-support decompositions, but it is based on a technique which integrates circuit graph analysis and BDD-based decomposition. The combination of the two approaches results in an algorithm which is more robust than a purely BDD-based one, and that improves both the quality of the results and the running time.

The fourth algorithm uses circuit graph analysis to obtain non-disjoint decompositions. We show that the problem of computing non-disjoint decompositions can be reduced to the problem of computing multiple-vertex dominators. We also prove that multiple-vertex dominators can be found in polynomial time. This result is important because there is no known polynomial time algorithm for computing all non-disjoint decompositions of a Boolean function.

The fifth algorithm provides an efficient means to decompose a function at the circuit graph level, by using information derived from a BDD representation. This is done without the expensive circuit re-synthesis normally associated with BDD-based decomposition approaches.

Finally we present two publications that resulted from the many detours we have taken along the winding path of our research.

Place, publisher, year, edition, pages
Stockholm: KTH, 2006. xi,176 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 06:06
Keyword
computer science, electronic system design, Boolean decomposition, binary decision diagram, logic synthesis, graph algorithm
National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-4135 (URN)
Public defence
2006-10-12, E, KTH Forum, Isafjordsgatan 39, Kista, 09:00
Opponent
Supervisors
Note
QC 20100909Available from: 2006-10-09 Created: 2006-10-09 Last updated: 2010-09-09Bibliographically approved

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