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Graph dominators in logic synthesis and verification
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
2004 (English)Licentiate thesis, comprehensive summary (Other scientific)
Abstract [en]

This work focuses on the usage of dominators in circuit graphs in order to reduce the complexity of synthesis and verification tasks. One of the contributions of this thesis is a new algorithm for computing multiple-vertex dominators in circuit graphs. Previous algorithms, based on single-vertex dominators suffer from their rare appearance in many circuits. The presented approach searches efficiently for multiple-vertex dominators in circuit graphs. It finds dominator relations, where algorithms for computing single-vertex dominators fail. Another contribution of this thesis is the application of dominators for combinational equivalence checking based on the arithmetic transform. Previous algorithms rely on representations providing an explicit or implicit disjoint function cover, which is usually excessive in memory requirements. The new algorithm allows a partitioned evaluation of the arithmetic transform directly on the circuit graph using dominator relations. The results show that the algorithm brings significant improvements in memory consumption for many benchmarks. Proper cuts are used in many areas of VLSI. They provide cut points, where a given problem can be split into two disjoint sub-problems. The algorithm proposed in this thesis efficiently detects proper cuts in a circuit graph and is based on a novel concept of a reduced dominator tree. The runtime of the algorithm is less than 0.4 seconds for the largest benchmark circuit. The final contribution of this thesis is the application of the proper cut algorithm as a structural method to decompose a Boolean function, represented by a circuit graph. In combination with a functional approach, it outperforms previous methods, which rely on functional decomposition only.

Place, publisher, year, edition, pages
2004.
Series
Trita-IMIT. LECS, ISSN 1651-4076 ; 2004:04
Keyword [en]
formal verification, logic synthesis, dominators, equivalence checking, decomposition
National Category
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-4293OAI: oai:DiVA.org:kth-4293DiVA: diva2:11683
Available from: 2007-03-01 Created: 2007-03-01 Last updated: 2012-03-20
List of papers
1. On-the-fly proper cut recognition based on circuit graph analysis
Open this publication in new window or tab >>On-the-fly proper cut recognition based on circuit graph analysis
2003 (English)In: Proceedings of NORCHIP'03, November 2003, Riga, Latvia, 2003Conference paper, Published paper (Other academic)
National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-6852 (URN)
Conference
NORCHIP'03, November 2003, Riga, Latvia
Note
QC 20110215Available from: 2007-03-01 Created: 2007-03-01 Last updated: 2011-02-15Bibliographically approved
2. Circuit-based evaluation ot the arithmetic transform of boolean functions
Open this publication in new window or tab >>Circuit-based evaluation ot the arithmetic transform of boolean functions
2002 (English)Conference paper, Published paper (Other academic)
Abstract [en]

In this paper we present a fast algorithm for evaluating the arithmetic transform of a Boolean function based on its circuit representation. The arithmetic transform has multiple applications in CAD, including the computation of signal probabilities and switching activities of circuit nets and the mapping of Boolean functions onto probabilistic hash values. Previous algorithms forevaluating the arithmetic transform required an orthogonal, non redundant representation of the function to be transformed in formof a disjoint function cover or a single BDD. We present a new algorithmt hat partitions the evaluation based on the dominator relationsof the circuit graph. Similar to the application of cut-pointsin combinational equivalence checking, the dominators are used to progressively simplify intermediate evaluation steps. As a result,the presented algorithm can handle larger circuits than previously possible. An extensive set of experiments on benchmark and industrialcircuits demonstrate the effectiveness of our approach.

National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-6853 (URN)
Conference
11th IEEE/ACM International Workshop on Logic & Synthesis, June 4-7, 2002, New Orleans, Louisiana, USA
Note
QC 20110215Available from: 2007-03-01 Created: 2007-03-01 Last updated: 2011-02-15Bibliographically approved
3. Fast algorithm for computing spectral transforms of boolean and multiple-valued functions on circuit representation
Open this publication in new window or tab >>Fast algorithm for computing spectral transforms of boolean and multiple-valued functions on circuit representation
2003 (English)In: 33RD INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 2003, 334-339 p.Conference paper, Published paper (Other academic)
Abstract [en]

In this paper we present a fast algorithm for computing the value of a spectral transform of Boolean or multiple-valued functions for a given assignment of input variables. Our current implementation is for arithmetic transform, because our work is primarily aimed at optimizing the performance of probabilistic verification methods. However, the presented technique is equally applicable for other discrete transforms, e.g. Walsh or Reed-Muller transforms. Previous methods for computing spectral transforms used truth tables, sum-of-product expressions, or various derivatives of decision diagrams. They were fundamentally limited by the excessive memory requirements of these data structures. We present a new algorithm that partitions the computation of the spectral transform based on the dominator relations of the circuit graph representing the function to be transformed As a result, the presented algorithm can handle larger functions than previously possible.

Series
International symp on multiple-valued logic - proceedings, ISSN 0195-623X
National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-6854 (URN)10.1109/ISMVL.2003.1201426 (DOI)000183282100050 ()
Conference
33rd International Symposium on Multiple-Valued Logic (ISMVL 2003) MEIJI UNIV, TOKYO, JAPAN, MAY 16-19, 2003
Note
QC 20110215Available from: 2007-03-01 Created: 2007-03-01 Last updated: 2012-08-22Bibliographically approved
4. Probabilistic verification based on function hashing
Open this publication in new window or tab >>Probabilistic verification based on function hashing
(English)Manuscript (Other academic)
National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-6855 (URN)
Note
QC 20110215Available from: 2007-03-01 Created: 2007-03-01 Last updated: 2011-02-15Bibliographically approved
5. A polynomial-time algorithm for computing bound sets
Open this publication in new window or tab >>A polynomial-time algorithm for computing bound sets
2006 (English)In: IEE Proceedings - Circuits Devices and Systems, ISSN 1350-2409, E-ISSN 1359-7000, Vol. 153, no 2, 179-184 p.Article in journal (Refereed) Published
Abstract [en]

An algorithm for computing bound sets of a Boolean function on its circuit representation is presented. The identification of bound sets is useful for many applications in logic synthesis, formal verification and testing. The presented algorithm computes bound sets by analysing dominator relations of the circuit. It has O(e . log n) worst-case complexity, where e is the number of edges and n is the number of vertices of the circuit graph. The experimental results show that the algorithm is efficient for large functions and allows computing bound sets for cases that were not possible to handle with previous methods.

Keyword
Algorithms, Computational complexity, Formal logic, Graph theory, Networks (circuits), Set theory
National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-6856 (URN)10.1049/ip-cds:20041261 (DOI)000237555600015 ()2-s2.0-33645000726 (Scopus ID)
Note

QC 20100927. Uppdaterad från Manuskript till Artikel (20100927).

QC 20150727

Available from: 2007-03-01 Created: 2007-03-01 Last updated: 2015-07-27Bibliographically approved
6. Roth-karp decomposition combining functional and structural techniques
Open this publication in new window or tab >>Roth-karp decomposition combining functional and structural techniques
2003 (English)In: Proceedings of International Workshop on Logic Synthesis, 2003, 18-23 p.Conference paper, Published paper (Other academic)
National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-6857 (URN)
Conference
International Workshop on Logic Synthesis, Laguna Beach, CA, May 2003
Note
QC 20110215Available from: 2007-03-01 Created: 2007-03-01 Last updated: 2011-02-15Bibliographically approved
7. Disjoint-support boolean decomposition combining functional and structural methods
Open this publication in new window or tab >>Disjoint-support boolean decomposition combining functional and structural methods
2004 (English)In: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 2004, 2004, 597-599 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents an algorithm for disjoint-support decomposition of Boolean functions which combines functional and structural approaches. First, a set of proper cut points is identified in the circuit by using dominator relations (structural method). Then, the circuit is partitioned along these cut points and a BDD-based decomposition is applied to the resulting smaller functions (functional method). Previous work on Boolean decomposition used only single methods and did not integrate a combined strategy. The experimental results show that the presented technique is more robust than a pure BDD-based approach and produces better-quality decompositions.

National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-6858 (URN)000221356700133 ()2-s2.0-2442599137 (Scopus ID)
Conference
Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004; Yokohama; Japan; 27 January 2004 through 30 January 2004;
Note

Uppdaterad från manuskript till konferensbidrag: 20100909 QC 20100909 QC 20150710

Available from: 2007-03-01 Created: 2007-03-01 Last updated: 2015-07-10Bibliographically approved

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Citation style
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