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GOI fabrication for Monolithic 3D integration
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH. (EKT)ORCID iD: 0000-0002-0446-2515
(English)In: Article in journal (Other academic) Submitted
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-221093OAI: oai:DiVA.org:kth-221093DiVA, id: diva2:1173654
Note

QC 20180115

Available from: 2018-01-12 Created: 2018-01-12 Last updated: 2018-01-15Bibliographically approved
In thesis
1. Fabrication of Group IV Semiconductors on Insulator for Monolithic 3D Integration
Open this publication in new window or tab >>Fabrication of Group IV Semiconductors on Insulator for Monolithic 3D Integration
2018 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The conventional 2D geometrical scaling of transistors is now facing many challenges in order to continue the performance enhancement while decreasing power consumption. The decrease in the device power consumption is related to the scaling of the power supply voltage (Vdd) and interconnects wiring length. In addition, monolithic three dimensional (M3D) integration in the form of vertically stacked devices, is a possible solution to increase the device density and reduce interconnect wiring length. Integrating strained germanium on insulator (sGeOI) pMOSFETs monolithically with strained silicon/silicon-germanium on insulator (sSOI/sSiGeOI) nMOSFETs can increase the device performance and packing density. Low temperature processing (<550 ºC) is essential as interconnects and strained layers limit the thermal budget in M3D. This thesis presents an experimental investigation of the low temperature (<450 ºC) fabrication of group IV semiconductor-on-insulator substrates with the focus on sGeOI and sSiGeOI fabrication processes compatible with M3D.

  To this aim, direct bonding was used to transfer the relaxed and strained semiconductor layers. The void formation dependencies of the oxide thickness, the surface treatment of the oxide and the post annealing time were fully examined. Low temperature SiGe epitaxy was investigated with the emphasis on the fabrication of Si0.5Ge0.5 strain-relaxed buffers (SRBs), etch-stop layer, and the device layer in the SiGeOI and GeOI process schemes. Ge epitaxial growth on Si as thick SRBs and thin device layers was investigated. Thick (500 nm-3 µm) and thin (<30 nm) relaxed GeOI substrates were fabricated. The latter was fabricated by continuous epitaxial growth of a 3-µm Ge (SRB)/Si0.5Ge0.5 (etch stop)/Ge (device layer) stack on Si. The fabricated long channel Ge pFETs from these GeOI substrates exhibit well-behaved IV characteristics with an effective mobility of 160 cm2/Vs.

  The planarization of SiO2 and SiGe SRBs for the fabrication of the strained GeOI and SiGeOI were accomplished by chemical mechanical polishing (CMP). Low temperature processes (<450 ºC) were developed for compressively strained GeOI layers (ɛ ~ -1.75 %, < 20 nm), which are used for high mobility and low power devices. For the first time, tensile strained Si0.5Ge0.5 (ɛ ~ 2.5 %, < 20 nm) films were successfully fabricated and transferred onto patterned substrates for 3D integration.

Place, publisher, year, edition, pages
Kungliga Tekniska högskolan, 2018. p. 139
Series
TRITA-EECS-AVL ; 2018:01
Keywords
monolithic three dimensional (M3D) integration, strained germanium on insulator (sGeOI) pMOSFETs, silicon/silicon-germanium on insulator (sSOI/sSiGeOI) nMOSFETs, Si0.5Ge0.5 strain-relaxed buffer (SRB), direct bonding, chemical mechanical polishing (CMP), compressively strained GeOI, tensile strained Si0.5Ge0.5OI
National Category
Nano Technology
Identifiers
urn:nbn:se:kth:diva-221097 (URN)978-91-7729-658-4 (ISBN)
Public defence
2018-02-16, Ka-Sal C, Electrum, Kungliga Tekniska högskolan, Kistagången 16, Kista, Stockholm, 10:00 (English)
Opponent
Supervisors
Note

QC 20180115

Available from: 2018-01-15 Created: 2018-01-12 Last updated: 2018-01-19Bibliographically approved

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Abedin, Ahmad

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