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xMAS-Based QoS Analysis Methodology
KTH, School of Information and Communication Technology (ICT), Electronics.ORCID iD: 0000-0003-0061-3475
2018 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 37, no 2, p. 364-377Article in journal (Refereed) Published
Abstract [en]

On-chip communication system design starting from a high-level model can facilitate formal verification of system properties, such as safety and deadlock freedom. Yet, analyzing its quality-of-service (QoS) property, in our context, per-flow delay bound, is an open challenge. Based on executable micro-architectural specification (xMAS) which is a formal framework modeling communication fabrics, we first present how to model a classic input-queuing virtual channel router using the xMAS primitives and then a QoS analysis methodology using network calculus (NC). Thanks to the precise semantics of the xMAS primitives, the router can be modeled in different variants, which cannot be otherwise captured by normal ad hoc box diagrams. The analysis methodology consists of three steps: 1) given network and flow knowledge, we first create a well-defined precise xMAS model for a specific application on a concrete on-chip network; 2) the specific xMAS model is then mapped to an NC graph (NCG) following a set of mapping rules; and 3) finally, existing QoS analysis techniques can be applied to analyze the NCG to obtain end-to-end delay bound per flow. We also show how to apply the technique to a typical all-to-one communication pattern on a binary-tree network and conduct an SoC case study, exemplifying the step-by-step analysis procedure and discussing the tightness of the results.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC , 2018. Vol. 37, no 2, p. 364-377
Keywords [en]
Design methodology, executable micro-architectural specification (xMAS), network calculus (NC), network-on-chip (NoC), quality-of-service (QoS)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-222173DOI: 10.1109/TCAD.2017.2706561ISI: 000422948500008Scopus ID: 2-s2.0-85040972387OAI: oai:DiVA.org:kth-222173DiVA, id: diva2:1180896
Note

QC 20180207

Available from: 2018-02-07 Created: 2018-02-07 Last updated: 2018-03-13Bibliographically approved

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Lu, Zhonghai

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