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Towards a Single Event Upset Detector Based on COTS FPGA
KTH, School of Information and Communication Technology (ICT), Electronics.
KTH, School of Information and Communication Technology (ICT), Electronics.
KTH, School of Information and Communication Technology (ICT), Electronics.ORCID iD: 0000-0002-8072-1742
2017 (English)In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC) / [ed] Nurmi, J Vesterbacka, M Wikner, JJ Alvandpour, A NielsenLonn, M Nielsen, IR, IEEE , 2017Conference paper, Published paper (Refereed)
Abstract [en]

The Single Event Upset Detector (SEUD) is 3U CubeSat payload experiment that aims to achieve radiation tolerant computing through detection and correction of SEU bit flips on COTS SRAM FPGAs. Our proposed self-healing architecture applies selective TMR, internal configuration memory scrubbing, and partial reconfiguration and intends to demonstrate a cost-effective alternative to Space-grade radiation hardened SRAM FPGAs. This paper presents an overview of the ongoing development of the SEUD architecture and when complete, the SEUD will be tested on board the KTH MIST student CubeSat that is targeting to be launched in late 2020.

Place, publisher, year, edition, pages
IEEE , 2017.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-223821ISI: 000425049100019OAI: oai:DiVA.org:kth-223821DiVA, id: diva2:1188020
Conference
2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS)
Note

QC 20180306

Available from: 2018-03-06 Created: 2018-03-06 Last updated: 2018-03-06Bibliographically approved

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