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Designing bio-inspired autonomous error-tolerant massively parallel computing architectures
KTH. Fudan University, China.ORCID iD: 0000-0002-7589-9749
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2017 (English)In: 30th IEEE International System on Chip Conference, SOCC 2017, IEEE Computer Society, 2017, p. 274-279Conference paper, Published paper (Refereed)
Abstract [en]

The scalable and massively parallel computing systems composed of many processors, which are connected on chips that will become more and more complex and unreliable. This paper presents a bio-inspired error tolerance framework and three design principles based on the Autonomous Error Tolerant (AET) architecture. A nearby error perception mechanism is carefully designed to detect faults and an initiative evolutions strategy is studied to handle unrecoverable errors. A circuit backup mechanism is proposed for generating an effective way by setting the routing rules to bypass the failed link or node to achieve fault tolerance capabilities. The print circuit board (PCB) prototype is designed and implemented based on a reconfigurable and scalable control-centric dual-core embedded processor (ReSC). Different testing programs associating fault-detection or self-backup schemes and routing algorithms are explored in the platform. Experimental results show that error perceptron can detect the faults and reassign the task for other remaining free and healthy AET cell through Network-on-chip (NoC) when faults occur at the AET cell. The system can complete error recovery within 3 seconds, the paper shows the error-tolerant capability of the proposed architecture is better than the conventional multi-modular redundant system.

Place, publisher, year, edition, pages
IEEE Computer Society, 2017. p. 274-279
Series
International System on Chip Conference, ISSN 2164-1676 ; 2017
Keywords [en]
Error-tolerant, Neuromorphic, NoC, Perceptron
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:kth:diva-225500DOI: 10.1109/SOCC.2017.8226057ISI: 000427618200051Scopus ID: 2-s2.0-85044290039ISBN: 9781538640333 OAI: oai:DiVA.org:kth-225500DiVA, id: diva2:1195819
Conference
30th IEEE International System on Chip Conference, SOCC 2017, Hotel Novotel, Munich, Germany, 5 September 2017 through 8 September 2017
Note

QC 20180406

Available from: 2018-04-06 Created: 2018-04-06 Last updated: 2018-04-11Bibliographically approved

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Ma, NingZou, Zhuo

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
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More styles
Language
  • de-DE
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Output format
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