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Pattern dependency in selective epitaxy of B-doped SiGe layers for advanced metal oxide semiconductor field effect transistors
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
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2008 (English)In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 103, no 5, 054907- p.Article in journal (Other academic) Published
Abstract [en]

This study presents investigations about the physical mechanisms, origin, and methods to control the pattern dependency in selective epitaxial growth of Si1-xGex (x=0.14-0.32) layers. It is shown with a comprehensive experimental study that the local Si coverage of individual chips on patterned wafers is the main parameter for the layer profile in the epitaxial growth. This was explained by the gas depletion of the growth species in the low velocity boundary layer over the wafer. The gas depletion radius around each oxide opening was in the centimeter range which is related to the boundary layer thickness. The results from these experiments were applied to grow Si0.75Ge0.25 layers with B concentration of 4x10(20) cm(-3) selectively for elevated source and drains in fully depleted ultrathin body silicon on insulator p metal oxide semiconductor field effect transistor (p-MOSFET) devices. The epitaxy control was maintained over a wide range of device sizes by optimized process parameters in combination with a wafer pattern design consisting of dummy features causing a uniform gas depletion over the chips on the wafer.

Place, publisher, year, edition, pages
2008. Vol. 103, no 5, 054907- p.
Keyword [en]
Doping (additives); Epitaxial growth; Optimization; Silicon wafers; Gas depletion; Pattern dependency; MOSFET devices
National Category
Condensed Matter Physics
Identifiers
URN: urn:nbn:se:kth:diva-7505DOI: 10.1063/1.2832631ISI: 000254025000108Scopus ID: 2-s2.0-40849126898OAI: oai:DiVA.org:kth-7505DiVA: diva2:12551
Note
QC 20100715. Tidigare titel: Pattern dependency in selective epitaxy of B-doped SiGe layers for advanced MOSFETs. Uppdaterad från manuskript till artikel 20100715.Available from: 2007-09-26 Created: 2007-09-26 Last updated: 2017-12-14Bibliographically approved
In thesis
1. Integration of epitaxial SiGe(C) layers in advanced CMOS devices
Open this publication in new window or tab >>Integration of epitaxial SiGe(C) layers in advanced CMOS devices
2007 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

Heteroepitaxial SiGe(C) layers have attracted immense attention as a material for performance boost in state of the art electronic devices during recent years. Alloying silicon with germanium and carbon add exclusive opportunities for strain and bandgap engineering. This work presents details of epitaxial growth using chemical vapor deposition (CVD), material characterization and integration of SiGeC layers in MOS devices.

Non-selective and selective epitaxial growth of Si1-x-yGexCy (0≤x≤0.30, 0≤y≤0.02) layers have been performed and optimized aimed for various metal oxide semiconductor field effect transistor (MOSFET) applications. A comprehensive experimental study was performed to investigate the growth of SiGeC layers. The incorporation of C into the SiGe matrix was shown to be strongly sensitive to the growth parameters. As a consequence, a much smaller epitaxial process window compared to SiGe epitaxy was obtained.

Incorporation of high boron concentrations (up to 1×1021 atoms/cm3) in SiGe layers aimed for recessed and/or elevated source/drain (S/D) junctions in pMOSFETs was also studied. HCl was used as Si etchant in the CVD reactor to create the recesses which was followed (in a single run) by selective epitaxy of B-doped SiGe.

The issue of pattern dependency behavior of selective epitaxial growth was studied in detail. It was shown that a complete removal of pattern dependency in selective SiGe growth using reduced pressure CVD is not likely. However, it was shown that the pattern dependency can be predicted since it is highly dependent on the local Si coverage of the substrate. The pattern dependency was most sensitive for Si coverage in the range 1-10%. In this range drastic changes in growth rate and composition was observed. The pattern dependency was explained by gas depletion inside the low velocity boundary layer.

Ni silicide is commonly used to reduce access resistance in S/D and gate areas of MOSFET devices. Therefore, the effect of carbon and germanium on the formation of NiSiGe(C) was studied. An improved thermal stability of Ni silicide was obtained when C is present in the SiGe layer.

Integration of SiGe(C) layers in various MOSFET devices was performed. In order to perform a relevant device research the dimensions of the investigated devices have to be in-line with the current technology nodes. A robust spacer gate technology was developed which enabled stable processing of transistors with gate lengths down to 45 nm.

SiGe(C) channels in ultra thin body (UTB) silicon on insulator (SOI) MOSFETs, with excellent performance down to 100 nm gate length was demonstrated. The integration of C in the channel of a MOSFET is interesting for future generations of ultra scaled devices where issues such as short channel effects (SCE), temperature budget, dopant diffusion and mobility will be extremely critical. A clear performance enhancement was obtained for both SiGe and SiGeC channels, which point out the potential of SiGe or SiGeC materials for UTB SOI devices.

Biaxially strained-Si (sSi) on SiGe virtual substrates (VS) as mobility boosters in nMOSFETs with gate length down to 80 nm was demonstrated. This concept was thoroughly investigated in terms of performance and leakage of the devices. In-situ doping of the relaxed SiGe was shown to be superior over implantation to suppress the junction leakage. A high channel doping could effectively suppress the source to drain leakage.

Place, publisher, year, edition, pages
Stockholm: KTH, 2007. xviii, 65 p.
Series
TRITA-ICT/MAP, 2007:7
Keyword
Silicon Germanium Carbon (SiGeC), Chemical Vapor Deposition (CVD), Epitaxy, Pattern Dependency, MOSFET, Mobility, Spacer Gate Technology
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-4498 (URN)
Public defence
2007-10-12, N2, Electrum 3, Isafjordsgatan 28, Kista, 10:00
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QC 20100715

Available from: 2007-09-26 Created: 2007-09-26 Last updated: 2016-02-19Bibliographically approved

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