A robust spacer gate process for deca-nanometer high-frequency MOSFETs
2006 (English)In: Microelectronic Engineering, ISSN 0167-9317, Vol. 83, no 3, 434-439 p.Article in journal (Refereed) Published
This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 pm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 mu S/mu m with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 mu A/mu m. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.
Place, publisher, year, edition, pages
2006. Vol. 83, no 3, 434-439 p.
Device processing; High frequency; Lithography; MOSFET; Nanoelectronics; Spacer technology
Condensed Matter Physics
IdentifiersURN: urn:nbn:se:kth:diva-7507DOI: 10.1016/j.mee.2005.11.008ISI: 000236318700008ScopusID: 2-s2.0-33244454516OAI: oai:DiVA.org:kth-7507DiVA: diva2:12553
QC 201007152007-09-262007-09-262012-03-22Bibliographically approved