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Hole mobility in ultrathin body SOI pMOSFETs with SiGe or SiGeC channels
KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-6705-1660
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
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2006 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 27, no 6, 466-468 p.Article in journal (Refereed) Published
Abstract [en]

The hole mobilities of SiGe and SiGeC channel pMOSFETs fabricated on ultrathin silicon-on-insulator substrates are investigated and compared with reference Si channel devices. The total thickness of the fully depleted Si/SiGe(C)/Si body structure is similar to 25 nm. All devices demonstrated a near ideal subthreshold behavior, and the drive current and mobility were increased with more than 60% for SiGe and SiGeC channels. When comparing SIMOX and UNIBOND substrates, no significant difference could be detected.

Place, publisher, year, edition, pages
2006. Vol. 27, no 6, 466-468 p.
Keyword [en]
Fully depleted (FD); Heterostructure; Mobility; MOSFETs; SiGe; SiGeC; Silicon-on-insulator (SOI) technology
National Category
Condensed Matter Physics
URN: urn:nbn:se:kth:diva-7508DOI: 10.1109/LED.2006.874763ISI: 000238070500014ScopusID: 2-s2.0-33744733389OAI: diva2:12554
QC 20100715Available from: 2007-09-26 Created: 2007-09-26 Last updated: 2010-09-16Bibliographically approved
In thesis
1. Integration of epitaxial SiGe(C) layers in advanced CMOS devices
Open this publication in new window or tab >>Integration of epitaxial SiGe(C) layers in advanced CMOS devices
2007 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

Heteroepitaxial SiGe(C) layers have attracted immense attention as a material for performance boost in state of the art electronic devices during recent years. Alloying silicon with germanium and carbon add exclusive opportunities for strain and bandgap engineering. This work presents details of epitaxial growth using chemical vapor deposition (CVD), material characterization and integration of SiGeC layers in MOS devices.

Non-selective and selective epitaxial growth of Si1-x-yGexCy (0≤x≤0.30, 0≤y≤0.02) layers have been performed and optimized aimed for various metal oxide semiconductor field effect transistor (MOSFET) applications. A comprehensive experimental study was performed to investigate the growth of SiGeC layers. The incorporation of C into the SiGe matrix was shown to be strongly sensitive to the growth parameters. As a consequence, a much smaller epitaxial process window compared to SiGe epitaxy was obtained.

Incorporation of high boron concentrations (up to 1×1021 atoms/cm3) in SiGe layers aimed for recessed and/or elevated source/drain (S/D) junctions in pMOSFETs was also studied. HCl was used as Si etchant in the CVD reactor to create the recesses which was followed (in a single run) by selective epitaxy of B-doped SiGe.

The issue of pattern dependency behavior of selective epitaxial growth was studied in detail. It was shown that a complete removal of pattern dependency in selective SiGe growth using reduced pressure CVD is not likely. However, it was shown that the pattern dependency can be predicted since it is highly dependent on the local Si coverage of the substrate. The pattern dependency was most sensitive for Si coverage in the range 1-10%. In this range drastic changes in growth rate and composition was observed. The pattern dependency was explained by gas depletion inside the low velocity boundary layer.

Ni silicide is commonly used to reduce access resistance in S/D and gate areas of MOSFET devices. Therefore, the effect of carbon and germanium on the formation of NiSiGe(C) was studied. An improved thermal stability of Ni silicide was obtained when C is present in the SiGe layer.

Integration of SiGe(C) layers in various MOSFET devices was performed. In order to perform a relevant device research the dimensions of the investigated devices have to be in-line with the current technology nodes. A robust spacer gate technology was developed which enabled stable processing of transistors with gate lengths down to 45 nm.

SiGe(C) channels in ultra thin body (UTB) silicon on insulator (SOI) MOSFETs, with excellent performance down to 100 nm gate length was demonstrated. The integration of C in the channel of a MOSFET is interesting for future generations of ultra scaled devices where issues such as short channel effects (SCE), temperature budget, dopant diffusion and mobility will be extremely critical. A clear performance enhancement was obtained for both SiGe and SiGeC channels, which point out the potential of SiGe or SiGeC materials for UTB SOI devices.

Biaxially strained-Si (sSi) on SiGe virtual substrates (VS) as mobility boosters in nMOSFETs with gate length down to 80 nm was demonstrated. This concept was thoroughly investigated in terms of performance and leakage of the devices. In-situ doping of the relaxed SiGe was shown to be superior over implantation to suppress the junction leakage. A high channel doping could effectively suppress the source to drain leakage.

Place, publisher, year, edition, pages
Stockholm: KTH, 2007. xviii, 65 p.
Silicon Germanium Carbon (SiGeC), Chemical Vapor Deposition (CVD), Epitaxy, Pattern Dependency, MOSFET, Mobility, Spacer Gate Technology
National Category
Condensed Matter Physics
urn:nbn:se:kth:diva-4498 (URN)
Public defence
2007-10-12, N2, Electrum 3, Isafjordsgatan 28, Kista, 10:00

QC 20100715

Available from: 2007-09-26 Created: 2007-09-26 Last updated: 2016-02-19Bibliographically approved

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