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Integration of epitaxial SiGe(C) layers in advanced CMOS devices
KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
2007 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

Heteroepitaxial SiGe(C) layers have attracted immense attention as a material for performance boost in state of the art electronic devices during recent years. Alloying silicon with germanium and carbon add exclusive opportunities for strain and bandgap engineering. This work presents details of epitaxial growth using chemical vapor deposition (CVD), material characterization and integration of SiGeC layers in MOS devices.

Non-selective and selective epitaxial growth of Si1-x-yGexCy (0≤x≤0.30, 0≤y≤0.02) layers have been performed and optimized aimed for various metal oxide semiconductor field effect transistor (MOSFET) applications. A comprehensive experimental study was performed to investigate the growth of SiGeC layers. The incorporation of C into the SiGe matrix was shown to be strongly sensitive to the growth parameters. As a consequence, a much smaller epitaxial process window compared to SiGe epitaxy was obtained.

Incorporation of high boron concentrations (up to 1×1021 atoms/cm3) in SiGe layers aimed for recessed and/or elevated source/drain (S/D) junctions in pMOSFETs was also studied. HCl was used as Si etchant in the CVD reactor to create the recesses which was followed (in a single run) by selective epitaxy of B-doped SiGe.

The issue of pattern dependency behavior of selective epitaxial growth was studied in detail. It was shown that a complete removal of pattern dependency in selective SiGe growth using reduced pressure CVD is not likely. However, it was shown that the pattern dependency can be predicted since it is highly dependent on the local Si coverage of the substrate. The pattern dependency was most sensitive for Si coverage in the range 1-10%. In this range drastic changes in growth rate and composition was observed. The pattern dependency was explained by gas depletion inside the low velocity boundary layer.

Ni silicide is commonly used to reduce access resistance in S/D and gate areas of MOSFET devices. Therefore, the effect of carbon and germanium on the formation of NiSiGe(C) was studied. An improved thermal stability of Ni silicide was obtained when C is present in the SiGe layer.

Integration of SiGe(C) layers in various MOSFET devices was performed. In order to perform a relevant device research the dimensions of the investigated devices have to be in-line with the current technology nodes. A robust spacer gate technology was developed which enabled stable processing of transistors with gate lengths down to 45 nm.

SiGe(C) channels in ultra thin body (UTB) silicon on insulator (SOI) MOSFETs, with excellent performance down to 100 nm gate length was demonstrated. The integration of C in the channel of a MOSFET is interesting for future generations of ultra scaled devices where issues such as short channel effects (SCE), temperature budget, dopant diffusion and mobility will be extremely critical. A clear performance enhancement was obtained for both SiGe and SiGeC channels, which point out the potential of SiGe or SiGeC materials for UTB SOI devices.

Biaxially strained-Si (sSi) on SiGe virtual substrates (VS) as mobility boosters in nMOSFETs with gate length down to 80 nm was demonstrated. This concept was thoroughly investigated in terms of performance and leakage of the devices. In-situ doping of the relaxed SiGe was shown to be superior over implantation to suppress the junction leakage. A high channel doping could effectively suppress the source to drain leakage.

Place, publisher, year, edition, pages
Stockholm: KTH , 2007. , xviii, 65 p.
Series
TRITA-ICT/MAP, 2007:7
Keyword [en]
Silicon Germanium Carbon (SiGeC), Chemical Vapor Deposition (CVD), Epitaxy, Pattern Dependency, MOSFET, Mobility, Spacer Gate Technology
National Category
Condensed Matter Physics
Identifiers
URN: urn:nbn:se:kth:diva-4498OAI: oai:DiVA.org:kth-4498DiVA: diva2:12557
Public defence
2007-10-12, N2, Electrum 3, Isafjordsgatan 28, Kista, 10:00
Opponent
Supervisors
Note

QC 20100715

Available from: 2007-09-26 Created: 2007-09-26 Last updated: 2016-02-19Bibliographically approved
List of papers
1. Growth of high quality epitaxial Si1-x-yGexCy layers by using chemical vapor deposition
Open this publication in new window or tab >>Growth of high quality epitaxial Si1-x-yGexCy layers by using chemical vapor deposition
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2004 (English)In: Applied Surface Science, ISSN 0169-4332, E-ISSN 1873-5584, Applied Surface Science, Vol. 224, no 1-4, 46-50 p.Article in journal (Refereed) Published
Abstract [en]

The epitaxial quality of non-selective and selective deposition of Si1-x-yGexCy (0 less than or equal to x less than or equal to 0.30, 0 less than or equal to y less than or equal to 0.02) layers has been optimized by using high-resolution reciprocal lattice mapping (HRRLM). The main goal was to incorporate a high amount of substitutional carbon atoms in Si or Si1-xGex matrix without creating defects. The carbon incorporation behavior was explained by chemical and kinetic effects of the reactant gases during epitaxial process. Although high quality epitaxial Si1-yCy layers can be deposited, lower electron mobility compared to Si layers was observed.

Keyword
Chemical vapor deposition; Epitaxy; High-resolution reciprocal lattice mapping; SiGeC alloys
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-7503 (URN)10.1016/j.apsusc.2003.08.026 (DOI)000189273900009 ()2-s2.0-1142280329 (Scopus ID)
Note
QC 20100715. Konferens: 1st International SiGe Technology and Device Meeting (ISTDM), Nagoya Univ Symposion, Nagoya, Japan, 2003.Available from: 2007-09-26 Created: 2007-09-26 Last updated: 2017-12-14Bibliographically approved
2. Integration of selective SiGe epitaxy for source/drain application in MOSFETs
Open this publication in new window or tab >>Integration of selective SiGe epitaxy for source/drain application in MOSFETs
2006 (English)In: Semiconductor Science and Technology, ISSN 0268-1242, E-ISSN 1361-6641, Vol. 22, no 1, 123-126 p.Article in journal (Refereed) Published
Abstract [en]

The integration of HCl chemical vapour etching and selective epitaxy by chemical vapour deposition of B-doped SiGe layers for recessed source/drain junction application has been studied. A temperature range of 850-900 degrees C is proposed to be suitable for the etch process in order to obtain a smooth Si surface. This point is crucial for the epitaxial quality of grown SiGe: B layers. The selectivity of the epitaxy was not as good for high B partial pressure. However, Si0.76Ge0.24 layers with a B concentration of 6 x 10(20) cm(-3) were selectively grown. The pattern dependence of the etch and epitaxy process was studied and a calibration of this versus Si coverage of the chip was performed.

National Category
Other Materials Engineering
Identifiers
urn:nbn:se:kth:diva-155412 (URN)10.1088/0268-1242/22/1/S29 (DOI)000243752500030 ()2-s2.0-34247545235 (Scopus ID)1424404614 (ISBN)9781424404612 (ISBN)
Conference
Third International SiGe Technology and Device Meeting, ISTDM 2006; Princeton, NJ; United States; 15 May 2006 through 17 May 2006
Note

Updated from conference paper to article.

QC 20141121

Available from: 2014-11-21 Created: 2014-11-05 Last updated: 2017-12-05Bibliographically approved
3. Pattern dependency in selective epitaxy of B-doped SiGe layers for advanced metal oxide semiconductor field effect transistors
Open this publication in new window or tab >>Pattern dependency in selective epitaxy of B-doped SiGe layers for advanced metal oxide semiconductor field effect transistors
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2008 (English)In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 103, no 5, 054907- p.Article in journal (Other academic) Published
Abstract [en]

This study presents investigations about the physical mechanisms, origin, and methods to control the pattern dependency in selective epitaxial growth of Si1-xGex (x=0.14-0.32) layers. It is shown with a comprehensive experimental study that the local Si coverage of individual chips on patterned wafers is the main parameter for the layer profile in the epitaxial growth. This was explained by the gas depletion of the growth species in the low velocity boundary layer over the wafer. The gas depletion radius around each oxide opening was in the centimeter range which is related to the boundary layer thickness. The results from these experiments were applied to grow Si0.75Ge0.25 layers with B concentration of 4x10(20) cm(-3) selectively for elevated source and drains in fully depleted ultrathin body silicon on insulator p metal oxide semiconductor field effect transistor (p-MOSFET) devices. The epitaxy control was maintained over a wide range of device sizes by optimized process parameters in combination with a wafer pattern design consisting of dummy features causing a uniform gas depletion over the chips on the wafer.

Keyword
Doping (additives); Epitaxial growth; Optimization; Silicon wafers; Gas depletion; Pattern dependency; MOSFET devices
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-7505 (URN)10.1063/1.2832631 (DOI)000254025000108 ()2-s2.0-40849126898 (Scopus ID)
Note
QC 20100715. Tidigare titel: Pattern dependency in selective epitaxy of B-doped SiGe layers for advanced MOSFETs. Uppdaterad från manuskript till artikel 20100715.Available from: 2007-09-26 Created: 2007-09-26 Last updated: 2017-12-14Bibliographically approved
4. The effect of carbon and germanium on phase transformation of nickel on Si1-x-yGexCy epitaxial layers
Open this publication in new window or tab >>The effect of carbon and germanium on phase transformation of nickel on Si1-x-yGexCy epitaxial layers
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2004 (English)In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 95, no 5, 2397- p.Article in journal (Refereed) Published
Abstract [en]

The influence of carbon and germanium on phase transformation and sheet resistance of Ni on epitaxially grown Si1-x-yGexCy (0less than or equal toxless than or equal to0.24 and 0less than or equal toyless than or equal to0.01) layers annealed in a temperature range of 360 to 900degreesC has been investigated. The role of strain relaxation or compensation in the reaction of Ni on Si1-x-yGexCy layers due to Ge or C out-diffusion to the underlying layer during the phase transformation has also been investigated. The formed NiSiGe layers were crystalline, with strong (020)/(013) growth orientation in the direction, but the thermal stability decreased rapidly with increasing Ge amount due to agglomeration. However, this thermal behavior was shifted to higher annealing temperatures when carbon was incorporated in the SiGe layers. A carbon accumulation at the interface of NiSiGeC/SiGeC has been observed even at low-temperature annealing, which is suggested to retard the phase transformation and agglomeration of Ni/SiGeC system.

Keyword
Agglomeration; Annealing; Carbon; Crystal orientation; Crystallography; Diffusion; Electron energy loss spectroscopy; Electron microscopes; Epitaxial growth; Germanium; Interfacial energy; Nickel; Phase transitions; Strain; Transmission electron microscopy; X ray diffraction analysis; Sheet resistance; Strain relaxation; Silicon alloys
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-7506 (URN)10.1063/1.1645996 (DOI)000189139600031 ()2-s2.0-12144288898 (Scopus ID)
Note
QC 20100715Available from: 2007-09-26 Created: 2007-09-26 Last updated: 2017-12-14Bibliographically approved
5. A robust spacer gate process for deca-nanometer high-frequency MOSFETs
Open this publication in new window or tab >>A robust spacer gate process for deca-nanometer high-frequency MOSFETs
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2006 (English)In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 3, 434-439 p.Article in journal (Refereed) Published
Abstract [en]

This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 pm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 mu S/mu m with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 mu A/mu m. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.

Keyword
Device processing; High frequency; Lithography; MOSFET; Nanoelectronics; Spacer technology
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-7507 (URN)10.1016/j.mee.2005.11.008 (DOI)000236318700008 ()2-s2.0-33244454516 (Scopus ID)
Note
QC 20100715Available from: 2007-09-26 Created: 2007-09-26 Last updated: 2017-12-14Bibliographically approved
6. Hole mobility in ultrathin body SOI pMOSFETs with SiGe or SiGeC channels
Open this publication in new window or tab >>Hole mobility in ultrathin body SOI pMOSFETs with SiGe or SiGeC channels
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2006 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 27, no 6, 466-468 p.Article in journal (Refereed) Published
Abstract [en]

The hole mobilities of SiGe and SiGeC channel pMOSFETs fabricated on ultrathin silicon-on-insulator substrates are investigated and compared with reference Si channel devices. The total thickness of the fully depleted Si/SiGe(C)/Si body structure is similar to 25 nm. All devices demonstrated a near ideal subthreshold behavior, and the drive current and mobility were increased with more than 60% for SiGe and SiGeC channels. When comparing SIMOX and UNIBOND substrates, no significant difference could be detected.

Keyword
Fully depleted (FD); Heterostructure; Mobility; MOSFETs; SiGe; SiGeC; Silicon-on-insulator (SOI) technology
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-7508 (URN)10.1109/LED.2006.874763 (DOI)000238070500014 ()2-s2.0-33744733389 (Scopus ID)
Note
QC 20100715Available from: 2007-09-26 Created: 2007-09-26 Last updated: 2017-12-14Bibliographically approved
7. Noise and mobility characteristics of bulk and fully depleted SOI pMOSFETs using Si or SiGe channels
Open this publication in new window or tab >>Noise and mobility characteristics of bulk and fully depleted SOI pMOSFETs using Si or SiGe channels
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2006 (English)In: ECS Transactions, ISSN 1938-5862, E-ISSN 1938-6737, Vol. 3, no 7, 67-72 p.Article in journal (Refereed) Published
Abstract [en]

State of the art bulk and fully depleted SOI Si and SiGe channel pMOSFET devices with gate lengths ranging from 0.1 to 200 μm were fabricated and analyzed in terms of drain current drivability, mobility and noise performance. In general the SOI devices demonstrated superior mobility and significantly reduced I/f noise compared to bulk devices maintaining a well controlled short channel effects due to the ultra thin body.

Keyword
Bulk devices; Drain current drivability; Gate lengths; Short channel effects; Carrier mobility; Channel capacity; Gates (transistor); Semiconducting silicon; Semiconducting silicon compounds; Signal noise measurement; Silicon on insulator technology; MOSFET devices
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-7509 (URN)10.1149/1.2355795 (DOI)2-s2.0-33846986504 (Scopus ID)
Note

QC 20100715. Konferens: SiGe and Ge: Materials, Processing, and Devices - 210th Electrochemical Society Meeting; Cancun; 29 October 2006 through 3 November 2006; Code 69092.

Available from: 2007-09-26 Created: 2007-09-26 Last updated: 2017-12-14Bibliographically approved
8. Leakage current reduction in 80 nm biaxially strained Si nMOSFETs on in-situ doped SiGe virtual substrates
Open this publication in new window or tab >>Leakage current reduction in 80 nm biaxially strained Si nMOSFETs on in-situ doped SiGe virtual substrates
Show others...
2007 (English)In: ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference 2008, 2007, 319-322 p.Conference paper, Published paper (Refereed)
Abstract [en]

We present a comprehensive study of biaxially strained (up to similar to 3 GPa stress) Si nMOSFETs down to 80 nm gatelength. Well behaved 80 nm devices with expected strain-induced electrical enhancement were demonstrated. Special emphasis was put on investigation of substrate junction leakage and source to drain leakage. In-situ doped wells and channel profiles demonstrated superior substrate junction leakage for the relaxed SiGe substrates compared to conventional implantation. The source to drain leakage in 80 nm devices was effectively reduced by increment of channel doping and rotation of the channel direction.

Series
Proceedings of the European Solid-State Device Research Conference, ISSN 1930-8876
Keyword
Drain current; Leakage currents; Semiconducting silicon; Semiconductor doping; Substrates; Channel doping; Drain leakage; Substrate junction leakage; MOSFET devices
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-7510 (URN)10.1109/ESSDERC.2007.4430942 (DOI)000252831900070 ()2-s2.0-39549092303 (Scopus ID)978-1-4244-1123-8 (ISBN)
Conference
ESSDERC07 - 2007 37th European Solid State Device Research Conference; Munich; 11 September 2007 through 13 September 2007; Category number 07EX1746; Code 71427
Note
QC 20100715Available from: 2007-09-26 Created: 2007-09-26 Last updated: 2010-09-16Bibliographically approved

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