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Exploiting Minipage-level Mapping to Improve Write Efficiency of NAND Flash
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2018 (English)In: 2018 IEEE INTERNATIONAL CONFERENCE ON NETWORKING, ARCHITECTURE AND STORAGE (NAS), Huazhong Univ Sci & Technol, Shenzhen Res Inst, Shenzhen 51800, Peoples R China. [Lv, Hao; Zhou, You; Wu, Fei; Xie, Changsheng] Huazhong Univ Sci & Technol, Wuhan Natl Lab Optoelect, Wuhan 430074, Hubei, Peoples R China. [Wu, Fei; Xie, Changsheng] Minist Educ, Key Lab Data Storage Syst, Wuhan 430074, Hubei, Peoples R China. [Xiao, Weijun] Virginia Commonwealth Univ, Dept Elect & Comp Engn, Richmond, VA 23284 USA. [He, Xubin] Temple Univ, Coll Sci & Technol, Philadelphia, PA 19122 USA. [Lu, Zhonghai] KTH Royal Inst Technol, Sch Informat & Commun Technol, S-10044 Stockholm, Sweden.: IEEE , 2018Conference paper, Published paper (Refereed)
Abstract [en]

Pushing NAND flash memory to higher density, manufacturers are aggressively enlarging the flash page size. However, the sizes of I/O requests in a wide range of scenarios do not grow accordingly. Since a page is the unit of flash read/write operations, traditional flash translation layers (FTLs) maintain the page mapping regularity. Hence, small random write requests become common, leading to extensive partial logical page writes. This write inefficiency significantly degrades the performance and increases the write amplification of flash storage. In this paper, we first propose a configurable mapping layer, called minipage, whose size is set to match I/O request sizes. The minipage-level mapping provides better flexibility in handling small writes at the cost of sequential read performance degradation and a larger mapping table. Then, we propose a new FTL, called PM-FTL, that exploits the minipage-level mapping to improve write efficiency and utilizes the page-level mapping to reduce the costs caused by the minipage-level mapping. Finally, trace-driven simulation results show that compared to traditional FTLs, PM-FTL reduces the write amplification and flash storage response time by an average of 33.4% and 19.1%, up to 57.7% and 34%, respectively, under 16KB flash pages and 4KB minipages.

Place, publisher, year, edition, pages
Huazhong Univ Sci & Technol, Shenzhen Res Inst, Shenzhen 51800, Peoples R China. [Lv, Hao; Zhou, You; Wu, Fei; Xie, Changsheng] Huazhong Univ Sci & Technol, Wuhan Natl Lab Optoelect, Wuhan 430074, Hubei, Peoples R China. [Wu, Fei; Xie, Changsheng] Minist Educ, Key Lab Data Storage Syst, Wuhan 430074, Hubei, Peoples R China. [Xiao, Weijun] Virginia Commonwealth Univ, Dept Elect & Comp Engn, Richmond, VA 23284 USA. [He, Xubin] Temple Univ, Coll Sci & Technol, Philadelphia, PA 19122 USA. [Lu, Zhonghai] KTH Royal Inst Technol, Sch Informat & Commun Technol, S-10044 Stockholm, Sweden.: IEEE , 2018.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-241347ISI: 000454656600017Scopus ID: 2-s2.0-85057570528OAI: oai:DiVA.org:kth-241347DiVA, id: diva2:1280411
Conference
13th IEEE International Conference on Networking, Architecture and Storage, NAS 2018; Chongqing; China; 11 October 2018 through 14 October 2018
Note

QC 20190118

Available from: 2019-01-18 Created: 2019-01-18 Last updated: 2019-01-18Bibliographically approved

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