Dominator-based Algorithms in Logic Synthesis and Verification
2007 (English)Doctoral thesis, monograph (Other academic)
Today's EDA (Electronic Design Automation) industry faces enormous challenges. Their primary cause is the tremendous increase of the complexity of modern digital designs. Graph algorithms are widely applied to solve various EDA problems. In particular, graph dominators, which provide information about the origin and the end of reconverging paths in a circuit graph, proved to be useful in various CAD (Computer Aided Design) applications such as equivalence checking, ATPG, technology mapping, and power optimization.
This thesis provides a study on graph dominators in logic synthesis and verification.
The thesis contributes a set of algorithms for computing dominators in circuit graphs. An algorithm is proposed for finding absolute dominators in circuit graphs. The achieved speedup of three orders of magnitude on several designs enables the computation of absolute dominators in large industrial designs in a few seconds. Moreover, the computation of single-vertex dominators in large multiple-output circuit graphs is considerably improved. The proposed algorithm reduces the overall runtime by efficiently recognizing and re-using isomorphic structures in dominator trees rooted at different outputs of the circuit graph. Finally, common multiple-vertex dominators are introduced. The algorithm to compute them is faster and finds more multiple-vertex dominators than previous approaches.
The thesis also proposes new dominator-based algorithms in the area of decomposition and combinational equivalence checking. A structural decomposition technique is introduced, which finds all simple-disjoint decompositions of a Boolean function which are reflected in the circuit graph. The experimental results demonstrate that the proposed technique outperforms state-of-the-art functional decomposition techniques. Finally, an approach to check the equivalence of two Boolean functions probabilistically is investigated. The proposed algorithm partitions the equivalence check employing dominators in the circuit graph. The experimental results confirm that, in comparison to traditional BDD-based equivalence checking methods, the memory consumption is considerably reduced by using the proposed technique.
Place, publisher, year, edition, pages
Stockholm: KTH , 2007. , xiv, 151 p.
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 2008:01
graph dominators, formal verification, logic synthesis, equivalence checking, decomposition
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-4579ISBN: 978-91-7178-804-7OAI: oai:DiVA.org:kth-4579DiVA: diva2:12952
2008-01-11, Sal D, KTH-Forum, Isafjordsgatan 39,, Kista, 13:00
Marques-Silva, Joao, Professor
QC 201008042007-12-142007-12-142010-08-04Bibliographically approved