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Design and Evaluation of Reduced Self-Capacitance Inductor for Fast-Switching SiC BJT dc/dc Converters
Warsaw Univ Technol, Inst Control & Ind Elect, Warsaw, Poland..
KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
Warsaw Univ Technol, Inst Control & Ind Elect, Warsaw, Poland..
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2012 (English)In: 2012 15TH INTERNATIONAL POWER ELECTRONICS AND MOTION CONTROL CONFERENCE (EPE/PEMC), IEEE , 2012Conference paper, Published paper (Refereed)
Abstract [en]

The paper presents design, measurements and evaluation of the inductor with reduced self-capacitance. As an reference inductor with the same parameters but non-optimized self-capacitance is chosen. Differences in the parasitic capacitance of the inductor are validated by four measurement methods and experimentally confirmed on a 2 kW, 100 kHz dc/dc converter with silicon carbide BJTs. When the low-capacitance inductor is applied the switching performance is better, especially high-frequency resonances are limited. Additionally, it was found that the power losses were reduced by approximately 20%.

Place, publisher, year, edition, pages
IEEE , 2012.
Keywords [en]
parasitic capacitance, inductor design, dc/dc converter, Silicon Carbide
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-245325ISI: 000337270600004OAI: oai:DiVA.org:kth-245325DiVA, id: diva2:1295644
Conference
15th International Power Electronics and Motion Control Conference and Exposition (EPE-PEMC ECCE Europe) Location: Novi Sad, SERBIA Date: SEP 04-06, 2012
Note

QC 20190312

Available from: 2019-03-12 Created: 2019-03-12 Last updated: 2019-08-21Bibliographically approved

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Nee, Hans-Peter

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