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On Designing PUF-Based TRNGs with Known Answer Tests
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.ORCID iD: 0000-0001-7382-9408
KTH, School of Electrical Engineering and Computer Science (EECS).
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems. Royal Inst Technol, Sch EECS, S-16440 Stockholm, Sweden..ORCID iD: 0000-0002-4691-2318
2018 (English)In: 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings / [ed] Nurmi, J Ellervee, P Mihhailov, J Jenihhin, M Tammemae, K, Institute of Electrical and Electronics Engineers (IEEE), 2018, article id 8573489Conference paper, Published paper (Refereed)
Abstract [en]

Random numbers are widely used in cryptographic algorithms and protocols. A faulty true random number generator (TRNG) may open a door into a system in spite of cryptographic protection. It is therefore important to design TRNGs so that they can be tested at different stages of their lifetime to assure their trustworthiness. In this paper, we propose a method for designing physical unclonable function (PUF)-based TRNGs which can be tested in-field by known answer tests. We present a prototype FPGA implementation of the proposed TRNG based on an arbiter PUF which passes all NIST 800-22 statistical tests and has the minimal entropy of 0.918 estimated according to NIST 800-90B recommendations. This is a nontrivial achievement given that arbiter PUFs are notoriously hard to place in a symmetric manner in FPGAs.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2018. article id 8573489
Keywords [en]
TRNG, PRNG, PUF, known answer test
National Category
Computer Sciences
Identifiers
URN: urn:nbn:se:kth:diva-249923DOI: 10.1109/NORCHIP.2018.8573489ISI: 000462188200011Scopus ID: 2-s2.0-85060609654ISBN: 9781538676561 (print)OAI: oai:DiVA.org:kth-249923DiVA, id: diva2:1307188
Conference
4th IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018; Tallinn; Estonia; 30 October 2018 through 31 October 2018
Note

QC 20190426

Available from: 2019-04-26 Created: 2019-04-26 Last updated: 2019-04-26Bibliographically approved

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Yu, YangDubrova, ElenaNäslund, MatsTao, Sha

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