Change search
ReferencesLink to record
Permanent link

Direct link
Functional Self-Test of DSP cores in a SOC
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
2007 (English)Independent thesis Basic level (professional degree), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

The rapid progress made in integrating enormous numbers of transistors on a single chip is making it possible for hardware designers to implement more complex hardware architectures in their designs. Nowadays digital telecommunication systems are implementing several forms of SOC (System-On-Chip) structures. These SOCs usually contain a microprocessor, several DSP cores (Digital-Signal-Processors), other hardware blocks, on-chip memories and peripherals.

As new IC process technologies are deployed, with decreasing geometrical dimensions, the probabilities of hardware faults to occur during operation are increasing. Testing SOCs is becoming a very complex issue due to the increasing complexity of the design and the increasing need of a test mechanism that is able to achieve acceptable fault coverage in a short test application time with low power consumption without the use of external logic testers.

As a part of the overall test strategy for a SOC, functional self-testing of a DSP core is considered in this project to be applied in the field. This test is used to verify whether fault indications in systems are caused by permanent hardware faults in the DSP. If so, the DSP where the fault is located needs to be taken out of operation, and the board it sits on will be later replaced. If not, the operational state can be restored, and the system will become fully functional again.

The main purpose of this project is to develop a functional self-test of a DSP core, and to evaluate the characteristics of the test. This project also involves proposing a scheme on how to apply a functional test on a DSP core in an embedded environment, and how to retrieve results from the test. The test program shall run at system speed.

To develop and measure the quality of the test program, two different coverage metrics were used. The first is the code coverage metric achieved by simulating the test program on the RTL representation of the DSP. The second metric used was the fault coverage achieved. The fault coverage of the test was calculated using a commercial Fault Simulator working on a gate-level representation of the DSP. The results achieved in this report show that this proposed approach can achieve acceptable levels of fault coverage in short execution time without the need for external testers which makes it possible to perform the self-test in the field. This approach has the unique property of not requiring any hardware modifications in the DSP design, and the ability of testing several DSPs in parallel.

Place, publisher, year, edition, pages
Kista: Tillämpad Informationsteknik , 2007. , 101 p.
Keyword [en]
functional testing, SOC, DSP, Self test, Embedded systems testing
National Category
Computer and Information Science
URN: urn:nbn:se:kth:diva-4612OAI: diva2:13089
Social and Behavioural Science, Law
Available from: 2008-01-23 Created: 2008-01-23 Last updated: 2010-07-13

Open Access in DiVA

fulltext(1342 kB)1549 downloads
File information
File name FULLTEXT01.pdfFile size 1342 kBChecksum SHA-1
Type fulltextMimetype application/pdf

By organisation
Microelectronics and Information Technology, IMIT
Computer and Information Science

Search outside of DiVA

GoogleGoogle Scholar
Total: 1549 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Total: 609 hits
ReferencesLink to record
Permanent link

Direct link