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Electrically robust ultralong nanowires of NiSi, Ni2Si and Ni31Si12
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-6705-1660
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0002-5845-3032
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
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2006 (English)In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 88, no 4, 043104- p.Article in journal (Refereed) Published
Abstract [en]

Mass fabrication of directly accessible, ultralong, uniform Si nanowires is realized by employing a controllable and reproducible method based on standard Si technology. High-conductivity polycrystalline Ni-silicide nanowires around 30 nm by 30 nm in cross section, able to support extremely high currents at similar to 10(8) A/cm(2), are obtained by means of solid-state reaction of the Si nanowires with subsequently deposited Ni films. By properly adjusting the Ni film thickness, NiSi, Ni2Si, and Ni31Si12 nanowires characterized with distinct resistivity and temperature coefficient of resistance are obtained. Upon annealing, the electrical continuity of the nanowires breaks at temperatures about 0.7 times the melting points of the silicides.

Place, publisher, year, edition, pages
2006. Vol. 88, no 4, 043104- p.
Keyword [en]
Annealing, Deposition, Electric resistance, Fabrication, Nanostructured materials, Polycrystalline materials, Silicon, Temperature distribution, Thin films
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-7948DOI: 10.1063/1.2168017ISI: 000234968600079Scopus ID: 2-s2.0-31544436663OAI: oai:DiVA.org:kth-7948DiVA: diva2:13136
Note
QC 20100910Available from: 2008-02-05 Created: 2008-02-05 Last updated: 2010-09-16Bibliographically approved
In thesis
1. Integration of silicide nanowires as Schottky barrier source/drain in FinFETs
Open this publication in new window or tab >>Integration of silicide nanowires as Schottky barrier source/drain in FinFETs
2008 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. As the device dimensions approach the fundamental limits, novel double/trigate device architecture such as FinFET is needed to guarantee the ultimate downscaling. Furthermore, Schottky barrier source/drain technology presents a promising solution to reducing the parasitic source/drain resistance in the FinFET. The ultimate goal of this thesis is to integrate Schottky barrier source/drain in FinFETs, with an emphasis on process development and integration towards competitive devices.

First, a robust sidewall transfer lithography (STL) technology is developed for mass fabrication of Si-nanowires in a controllable manner. A scalable self-aligned silicide (SALICIDE) process for Pt-silicides is also developed. Directly accessible and uniform NWs of Ni- and Pt-silicides are routinely fabricated by combining STL and SALICIDE. The silicide NWs are characterized by resistivity values comparable to those of their thin–film counterparts.

Second, a systematic experimental study is performed for dopant segregation (DS) at the PtSi/Si and NiSi/Si interfaces in order to modulate the effective SBHs needed for competitive FinFETs. Two complementary schemes SIDS (silicidation induced dopant segregation) and SADS (silicide as diffusion source) are compared, and both yield substantial SBH modifications for both polarities of Schottky diodes (i.e. φbn and φbp).

Third, Schottky barrier source/drain MOSFETs are fabricated in UTB-SOI. With PtSi that is usually used as the Schottky barrier source/drain for p-channel SB-MOSFETs, DS with appropriate dopants leads to excellent performance for both types of SBMOSFETs. However, a large variation in position of the PtSi/Si interface with reference to the gate edge (i.e., underlap) along the gate width is evidenced by TEM.

Finally, integration of PtSi NWs in FinFETs is carried out by combining the STL technology, the Pt-SALICIDE process and the DS technology, all developed during the course of this thesis work. The performance of the p-channel FinFETs is improved by DS with B, confirming the SB-FinFET concept despite device performance fluctuations mostly likely due to the presence of the PtSi-to-gate underlap.

Place, publisher, year, edition, pages
Stockholm: KTH, 2008. xvi, 80 p.
Series
Trita-ICT/MAP AVH, ISSN 1653-7610 ; 2008:02
Keyword
CMOS technology, MOSFET, FinFET, Schottky diode, Schottky barrier soure/drain, silicide, SALICIDE, SOI, multiple-gate, nanowire, sidewall transfer lithography
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-4628 (URN)
Public defence
2008-02-19, Sal N1, KTH-Electrum 3, Isafjordsgatan 28, Kista, 10:00
Opponent
Supervisors
Note
QC 20100923Available from: 2008-02-05 Created: 2008-02-05 Last updated: 2010-09-23Bibliographically approved

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Hellström, Per Erik

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