Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Robust, scalable self-aligned platinum silicide process
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0002-5845-3032
Uppsala University, Ångström Laboratory.
2006 (English)In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 88, no 14, 142114- p.Article in journal (Refereed) Published
Abstract [en]

A robust, scalable PtSix process is developed. The process consists of two consecutive annealing steps in a single run; the first is silicidation of Pt films on Si substrates carried out in N-2, whereas the second is surface oxidation of the resultant PtSix in O-2. By adequately adjusting the temperature during the oxidation step, a protective SiOx hard mask forms on PtSix of different thicknesses and compositions. Such a surface oxidation is absent for Pt on SiO2 isolation, which is crucial for the subsequent selective wet etch for a self-aligned process. Ultralong PtSix nanowires are fabricated using this robust self-aligned process.

Place, publisher, year, edition, pages
2006. Vol. 88, no 14, 142114- p.
Keyword [en]
Annealing, Composition, Etching, Oxidation, Platinum compounds, Substrates, Platinum silicide processes, Pt Six nanowires, Surface oxidations, Wet etch
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-7950DOI: 10.1063/1.2194313ISI: 000236612000055Scopus ID: 2-s2.0-33646692940OAI: oai:DiVA.org:kth-7950DiVA: diva2:13138
Note
QC 20100923Available from: 2008-02-05 Created: 2008-02-05 Last updated: 2017-12-14Bibliographically approved
In thesis
1. Integration of silicide nanowires as Schottky barrier source/drain in FinFETs
Open this publication in new window or tab >>Integration of silicide nanowires as Schottky barrier source/drain in FinFETs
2008 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. As the device dimensions approach the fundamental limits, novel double/trigate device architecture such as FinFET is needed to guarantee the ultimate downscaling. Furthermore, Schottky barrier source/drain technology presents a promising solution to reducing the parasitic source/drain resistance in the FinFET. The ultimate goal of this thesis is to integrate Schottky barrier source/drain in FinFETs, with an emphasis on process development and integration towards competitive devices.

First, a robust sidewall transfer lithography (STL) technology is developed for mass fabrication of Si-nanowires in a controllable manner. A scalable self-aligned silicide (SALICIDE) process for Pt-silicides is also developed. Directly accessible and uniform NWs of Ni- and Pt-silicides are routinely fabricated by combining STL and SALICIDE. The silicide NWs are characterized by resistivity values comparable to those of their thin–film counterparts.

Second, a systematic experimental study is performed for dopant segregation (DS) at the PtSi/Si and NiSi/Si interfaces in order to modulate the effective SBHs needed for competitive FinFETs. Two complementary schemes SIDS (silicidation induced dopant segregation) and SADS (silicide as diffusion source) are compared, and both yield substantial SBH modifications for both polarities of Schottky diodes (i.e. φbn and φbp).

Third, Schottky barrier source/drain MOSFETs are fabricated in UTB-SOI. With PtSi that is usually used as the Schottky barrier source/drain for p-channel SB-MOSFETs, DS with appropriate dopants leads to excellent performance for both types of SBMOSFETs. However, a large variation in position of the PtSi/Si interface with reference to the gate edge (i.e., underlap) along the gate width is evidenced by TEM.

Finally, integration of PtSi NWs in FinFETs is carried out by combining the STL technology, the Pt-SALICIDE process and the DS technology, all developed during the course of this thesis work. The performance of the p-channel FinFETs is improved by DS with B, confirming the SB-FinFET concept despite device performance fluctuations mostly likely due to the presence of the PtSi-to-gate underlap.

Place, publisher, year, edition, pages
Stockholm: KTH, 2008. xvi, 80 p.
Series
Trita-ICT/MAP AVH, ISSN 1653-7610 ; 2008:02
Keyword
CMOS technology, MOSFET, FinFET, Schottky diode, Schottky barrier soure/drain, silicide, SALICIDE, SOI, multiple-gate, nanowire, sidewall transfer lithography
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-4628 (URN)
Public defence
2008-02-19, Sal N1, KTH-Electrum 3, Isafjordsgatan 28, Kista, 10:00
Opponent
Supervisors
Note
QC 20100923Available from: 2008-02-05 Created: 2008-02-05 Last updated: 2010-09-23Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Search in DiVA

By author/editor
Zhang, ZhenZhang, Shi-LiÖstling, Mikael
By organisation
Integrated Devices and Circuits
In the same journal
Applied Physics Letters
Other Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 154 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf