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Performance fluctuation of FinFETs with Schottky barrier source/drain
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Uppsala University, Ångström Laboratory.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-6705-1660
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2008 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 5, 506-508 p.Article in journal (Refereed) Published
Abstract [en]

A considerable performance fluctuation of FinFETs featuring PtSi-based Schottky barrier source/drain is found. The Fin-channels measure 27-nm tall and 35-nm wide. Investigation of similarly processed transistors of broad gate-widths reveals a large variation in the position of the PtSi/Si interface with reference to the gate edge along the gate width. This variation suggests an uneven underlap between the PtSi and the gate from device to device for the FinFETs, since essentially only one silicide grain would be in contact with each Fin-channel at the PtSi/Si interface. The size of the underlap is expected to sensitively affect the performance of the FinFETs.

Place, publisher, year, edition, pages
2008. Vol. 29, no 5, 506-508 p.
Keyword [en]
FinFETs, gate underlap, MOSFETs, platinum silicide PtSi, Schottky barrier source/drain (SB-S/D), transmission electron microscopy (TEM)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-7954DOI: 10.1109/LED.2008.920284ISI: 000255317400027Scopus ID: 2-s2.0-43549106338OAI: oai:DiVA.org:kth-7954DiVA: diva2:13142
Note
QC 20100923. Uppdaterad från submitted till published (20100923).Available from: 2008-02-05 Created: 2008-02-05 Last updated: 2017-12-14Bibliographically approved
In thesis
1. Integration of silicide nanowires as Schottky barrier source/drain in FinFETs
Open this publication in new window or tab >>Integration of silicide nanowires as Schottky barrier source/drain in FinFETs
2008 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. As the device dimensions approach the fundamental limits, novel double/trigate device architecture such as FinFET is needed to guarantee the ultimate downscaling. Furthermore, Schottky barrier source/drain technology presents a promising solution to reducing the parasitic source/drain resistance in the FinFET. The ultimate goal of this thesis is to integrate Schottky barrier source/drain in FinFETs, with an emphasis on process development and integration towards competitive devices.

First, a robust sidewall transfer lithography (STL) technology is developed for mass fabrication of Si-nanowires in a controllable manner. A scalable self-aligned silicide (SALICIDE) process for Pt-silicides is also developed. Directly accessible and uniform NWs of Ni- and Pt-silicides are routinely fabricated by combining STL and SALICIDE. The silicide NWs are characterized by resistivity values comparable to those of their thin–film counterparts.

Second, a systematic experimental study is performed for dopant segregation (DS) at the PtSi/Si and NiSi/Si interfaces in order to modulate the effective SBHs needed for competitive FinFETs. Two complementary schemes SIDS (silicidation induced dopant segregation) and SADS (silicide as diffusion source) are compared, and both yield substantial SBH modifications for both polarities of Schottky diodes (i.e. φbn and φbp).

Third, Schottky barrier source/drain MOSFETs are fabricated in UTB-SOI. With PtSi that is usually used as the Schottky barrier source/drain for p-channel SB-MOSFETs, DS with appropriate dopants leads to excellent performance for both types of SBMOSFETs. However, a large variation in position of the PtSi/Si interface with reference to the gate edge (i.e., underlap) along the gate width is evidenced by TEM.

Finally, integration of PtSi NWs in FinFETs is carried out by combining the STL technology, the Pt-SALICIDE process and the DS technology, all developed during the course of this thesis work. The performance of the p-channel FinFETs is improved by DS with B, confirming the SB-FinFET concept despite device performance fluctuations mostly likely due to the presence of the PtSi-to-gate underlap.

Place, publisher, year, edition, pages
Stockholm: KTH, 2008. xvi, 80 p.
Series
Trita-ICT/MAP AVH, ISSN 1653-7610 ; 2008:02
Keyword
CMOS technology, MOSFET, FinFET, Schottky diode, Schottky barrier soure/drain, silicide, SALICIDE, SOI, multiple-gate, nanowire, sidewall transfer lithography
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-4628 (URN)
Public defence
2008-02-19, Sal N1, KTH-Electrum 3, Isafjordsgatan 28, Kista, 10:00
Opponent
Supervisors
Note
QC 20100923Available from: 2008-02-05 Created: 2008-02-05 Last updated: 2010-09-23Bibliographically approved

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