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Integration of silicide nanowires as Schottky barrier source/drain in FinFETs
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
2008 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. As the device dimensions approach the fundamental limits, novel double/trigate device architecture such as FinFET is needed to guarantee the ultimate downscaling. Furthermore, Schottky barrier source/drain technology presents a promising solution to reducing the parasitic source/drain resistance in the FinFET. The ultimate goal of this thesis is to integrate Schottky barrier source/drain in FinFETs, with an emphasis on process development and integration towards competitive devices.

First, a robust sidewall transfer lithography (STL) technology is developed for mass fabrication of Si-nanowires in a controllable manner. A scalable self-aligned silicide (SALICIDE) process for Pt-silicides is also developed. Directly accessible and uniform NWs of Ni- and Pt-silicides are routinely fabricated by combining STL and SALICIDE. The silicide NWs are characterized by resistivity values comparable to those of their thin–film counterparts.

Second, a systematic experimental study is performed for dopant segregation (DS) at the PtSi/Si and NiSi/Si interfaces in order to modulate the effective SBHs needed for competitive FinFETs. Two complementary schemes SIDS (silicidation induced dopant segregation) and SADS (silicide as diffusion source) are compared, and both yield substantial SBH modifications for both polarities of Schottky diodes (i.e. φbn and φbp).

Third, Schottky barrier source/drain MOSFETs are fabricated in UTB-SOI. With PtSi that is usually used as the Schottky barrier source/drain for p-channel SB-MOSFETs, DS with appropriate dopants leads to excellent performance for both types of SBMOSFETs. However, a large variation in position of the PtSi/Si interface with reference to the gate edge (i.e., underlap) along the gate width is evidenced by TEM.

Finally, integration of PtSi NWs in FinFETs is carried out by combining the STL technology, the Pt-SALICIDE process and the DS technology, all developed during the course of this thesis work. The performance of the p-channel FinFETs is improved by DS with B, confirming the SB-FinFET concept despite device performance fluctuations mostly likely due to the presence of the PtSi-to-gate underlap.

Place, publisher, year, edition, pages
Stockholm: KTH , 2008. , xvi, 80 p.
Series
Trita-ICT/MAP AVH, ISSN 1653-7610 ; 2008:02
Keyword [en]
CMOS technology, MOSFET, FinFET, Schottky diode, Schottky barrier soure/drain, silicide, SALICIDE, SOI, multiple-gate, nanowire, sidewall transfer lithography
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-4628OAI: oai:DiVA.org:kth-4628DiVA: diva2:13143
Public defence
2008-02-19, Sal N1, KTH-Electrum 3, Isafjordsgatan 28, Kista, 10:00
Opponent
Supervisors
Note
QC 20100923Available from: 2008-02-05 Created: 2008-02-05 Last updated: 2010-09-23Bibliographically approved
List of papers
1. A novel self-aligned process for platinum silicide nanowires
Open this publication in new window or tab >>A novel self-aligned process for platinum silicide nanowires
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2006 (English)In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 11-12, 2107-2111 p.Article in journal (Refereed) Published
Abstract [en]

Directly accessible, ultralong, uniform platinum silicide nanowires in PtSi and Pt2Si are mass-fabricated by combining a sidewall transfer lithography (STL) technology and a self-aligned silicide process. The STL technology is based on standard Si technology. The self-aligned platinum silicide (PtSix) process consists of two sequential steps in a single run: a silicidation step in N-2 to ensure a controllable silicide formation followed by an oxidation step in O-2 to form a reliable protective SiOx layer on top of the grown PtSix. The achieved nanowires are characterised by a low resistivity: 26 +/- 3 and 34 +/- 2 mu Omega cm for the Pt2Si- and PtSi-dominated nanowires.

Keyword
sidewall transfer lithography; self-aligned process; nanowire; platinum silicide
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-7947 (URN)10.1016/j.mee.2006.09.032 (DOI)000243315700013 ()2-s2.0-33751233878 (Scopus ID)
Note
QC 20100824Available from: 2008-02-05 Created: 2008-02-05 Last updated: 2017-12-14Bibliographically approved
2. Electrically robust ultralong nanowires of NiSi, Ni2Si and Ni31Si12
Open this publication in new window or tab >>Electrically robust ultralong nanowires of NiSi, Ni2Si and Ni31Si12
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2006 (English)In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 88, no 4, 043104- p.Article in journal (Refereed) Published
Abstract [en]

Mass fabrication of directly accessible, ultralong, uniform Si nanowires is realized by employing a controllable and reproducible method based on standard Si technology. High-conductivity polycrystalline Ni-silicide nanowires around 30 nm by 30 nm in cross section, able to support extremely high currents at similar to 10(8) A/cm(2), are obtained by means of solid-state reaction of the Si nanowires with subsequently deposited Ni films. By properly adjusting the Ni film thickness, NiSi, Ni2Si, and Ni31Si12 nanowires characterized with distinct resistivity and temperature coefficient of resistance are obtained. Upon annealing, the electrical continuity of the nanowires breaks at temperatures about 0.7 times the melting points of the silicides.

Keyword
Annealing, Deposition, Electric resistance, Fabrication, Nanostructured materials, Polycrystalline materials, Silicon, Temperature distribution, Thin films
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-7948 (URN)10.1063/1.2168017 (DOI)000234968600079 ()2-s2.0-31544436663 (Scopus ID)
Note
QC 20100910Available from: 2008-02-05 Created: 2008-02-05 Last updated: 2017-12-14Bibliographically approved
3. Ni2Si nanowires of extraordinarily low resistivity
Open this publication in new window or tab >>Ni2Si nanowires of extraordinarily low resistivity
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2006 (English)In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 88, no 21, 213103- p.Article in journal (Refereed) Published
Abstract [en]

Ultralong, polycrystalline Ni2Si nanowires are fabricated by combining sidewall transfer lithography with self-aligned silicidation. Upon formation at 500 degrees C, the nanowires that are 400 mu m long with a rectangular cross section of 37.5 by 25.3 nm are characterized by a resistivity of 25 +/- 1 mu Omega cm which is similar to the value for Ni2Si thin films. Further annealing at 800 degrees C results in an extraordinarily low wire resistivity of 10 mu Omega cm. Such a drastic decrease in resistivity is attributed to a significant grain growth and a low density of defects in the nanowires.

Keyword
Annealing, Crystal defects, Grain growth, Lithography, Nickel compounds, Polycrystalline materials, Silicon compounds, Density of defects, Rectangular cross section, Sidewall transfer lithography, Silicidation
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-7949 (URN)10.1063/1.2207222 (DOI)000237846800072 ()2-s2.0-33744518182 (Scopus ID)
Note
QC 20100923Available from: 2008-02-05 Created: 2008-02-05 Last updated: 2017-12-14Bibliographically approved
4. Robust, scalable self-aligned platinum silicide process
Open this publication in new window or tab >>Robust, scalable self-aligned platinum silicide process
2006 (English)In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 88, no 14, 142114- p.Article in journal (Refereed) Published
Abstract [en]

A robust, scalable PtSix process is developed. The process consists of two consecutive annealing steps in a single run; the first is silicidation of Pt films on Si substrates carried out in N-2, whereas the second is surface oxidation of the resultant PtSix in O-2. By adequately adjusting the temperature during the oxidation step, a protective SiOx hard mask forms on PtSix of different thicknesses and compositions. Such a surface oxidation is absent for Pt on SiO2 isolation, which is crucial for the subsequent selective wet etch for a self-aligned process. Ultralong PtSix nanowires are fabricated using this robust self-aligned process.

Keyword
Annealing, Composition, Etching, Oxidation, Platinum compounds, Substrates, Platinum silicide processes, Pt Six nanowires, Surface oxidations, Wet etch
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-7950 (URN)10.1063/1.2194313 (DOI)000236612000055 ()2-s2.0-33646692940 (Scopus ID)
Note
QC 20100923Available from: 2008-02-05 Created: 2008-02-05 Last updated: 2017-12-14Bibliographically approved
5. Schottky-barrier height tuning by means of ion implantation into preformed silicide films followed by drive-in anneal
Open this publication in new window or tab >>Schottky-barrier height tuning by means of ion implantation into preformed silicide films followed by drive-in anneal
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2007 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 28, no 7, 565-568 p.Article in journal (Refereed) Published
Abstract [en]

An experimental study on Schottky-barrier height (SBH) tuning using ion implantation followed by drive-in anneal of As, B, In, and P in preformed NiSi and PtSi films is presented. Measured on B-implanted NiSi and PtSi Schottky diodes, the effective SBH on n-type Si is altered to similar to 1.0 eV. For As- and P-implanted diodes, the SBH on p-type Si can be tuned to around 0.9 eV The process window for the most pronounced SBH modification is dopant dependent.

Keyword
dopant segregation, Schottky barrier (SB) lowering, Schottky diode, silicide
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-7951 (URN)10.1109/LED.2007.900295 (DOI)000247643900009 ()2-s2.0-34447282256 (Scopus ID)
Note
QC 20100923Available from: 2008-02-05 Created: 2008-02-05 Last updated: 2017-12-14Bibliographically approved
6. A comparative study of two different schemes to dopant segregation at NiSi/Si and PtSi/Si interfaces for Schottky barrier height lowering
Open this publication in new window or tab >>A comparative study of two different schemes to dopant segregation at NiSi/Si and PtSi/Si interfaces for Schottky barrier height lowering
2008 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 55, no 1, 396-403 p.Article in journal (Refereed) Published
Abstract [en]

An experimental study is presented to compare two different schemes used to incorporate a high concentration of dopants at the silicide/silicon interface for NiSi and PtSi, i.e., dopant segregation, with the purpose of lowering the Schottky barrier height (SBH) of the contact systems. Specifically, the interfacial dopant is introduced either through silicidation-induced dopant segregation (SIDS) or by silicide as diffusion source (SADS). For the latter, a postimplantation drive-in anneal is needed. For both silicide systems, the dopant segregation gives rise to a predominant effect, leading to an effective SBH that is independent of the original SBHs of PtSi and NiSi, which differs by 0.2 eV. Scheme SUDS is relatively simple in processing, but the silicidation process is dopant-dependent, leading to local variations of silicide formation. Scheme SADS addresses the adverse effect of dopant on silicidation by separating silicidation from dopant incorporation.

Keyword
dopant segregation; Schottky barrier (SB) lowering; Schottky diode; silicide
National Category
Computer and Information Science
Identifiers
urn:nbn:se:kth:diva-7952 (URN)10.1109/TED.2007.911080 (DOI)000252059000040 ()2-s2.0-37749045251 (Scopus ID)
Note
QC 20100819Available from: 2008-02-05 Created: 2008-02-05 Last updated: 2017-12-14Bibliographically approved
7. SB-MOSFETs in UTB-SOI featuring PtSi source/drain with dopant segregation
Open this publication in new window or tab >>SB-MOSFETs in UTB-SOI featuring PtSi source/drain with dopant segregation
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2008 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 1, 125-127 p.Article in journal (Refereed) Published
Abstract [en]

MOSFETs of both polarities with PtSi-based Schottky-barrier source/drain (S/D) have been fabricated in ultrathin-body Si-on-insulator. The PtSi is formed in the S/D regions without lateral silicide growth under the gate spacers. This design leads to a 30-nm underlap between the PtSi-Si contacts and the gate edges resulting in low drive currents. Despite the underlap, excellent performance is achieved for both types of MOSFETs with large drive currents and low leakage by means of dopant segregation through As and B implantation into the PtSi followed by drive-in annealing at low temperatures.

Keyword
dopant segregation (DS), MOSFETs, platinum silicide, Schottky-barrier lowering, Schottky-barrier source/drain (SB-S/D), ultrathin-body Si-on-insulator (UTB-SOI)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-7953 (URN)10.1109/LED.2007.911990 (DOI)000252098100038 ()2-s2.0-37549025369 (Scopus ID)
Note
QC 20100923Available from: 2008-02-05 Created: 2008-02-05 Last updated: 2017-12-14Bibliographically approved
8. Performance fluctuation of FinFETs with Schottky barrier source/drain
Open this publication in new window or tab >>Performance fluctuation of FinFETs with Schottky barrier source/drain
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2008 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 5, 506-508 p.Article in journal (Refereed) Published
Abstract [en]

A considerable performance fluctuation of FinFETs featuring PtSi-based Schottky barrier source/drain is found. The Fin-channels measure 27-nm tall and 35-nm wide. Investigation of similarly processed transistors of broad gate-widths reveals a large variation in the position of the PtSi/Si interface with reference to the gate edge along the gate width. This variation suggests an uneven underlap between the PtSi and the gate from device to device for the FinFETs, since essentially only one silicide grain would be in contact with each Fin-channel at the PtSi/Si interface. The size of the underlap is expected to sensitively affect the performance of the FinFETs.

Keyword
FinFETs, gate underlap, MOSFETs, platinum silicide PtSi, Schottky barrier source/drain (SB-S/D), transmission electron microscopy (TEM)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-7954 (URN)10.1109/LED.2008.920284 (DOI)000255317400027 ()2-s2.0-43549106338 (Scopus ID)
Note
QC 20100923. Uppdaterad från submitted till published (20100923).Available from: 2008-02-05 Created: 2008-02-05 Last updated: 2017-12-14Bibliographically approved

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