Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Configurable FFT Processor Using Dynamically Reconfigurable Resource Arrays
TU Wien, Inst Comp Technol, Gusshausstr 27-29-384, A-1040 Vienna, Austria.;Bahria Univ, Dept Elect Engn, Shangrilla Rd,Sect E-8, Islamabad, Pakistan..
KTH, School of Information and Communication Technology (ICT).
KTH, School of Information and Communication Technology (ICT).ORCID iD: 0000-0003-0565-9376
2019 (English)In: Journal of Signal Processing Systems, ISSN 1939-8018, E-ISSN 1939-8115, Vol. 91, no 5, p. 459-473Article in journal (Refereed) Published
Abstract [en]

This paper presents results of using a Coarse Grain Reconfigurable Architecture called DRRA (Dynamically Reconfigurable Resource Array) for FFT implementations varying in order and degree of parallelism using radix-2 decimation in time (DIT). The DRRA fabric is extended with memory architecture to be able to deal with data-sets much larger than what can be accommodated in the register files of DRRA. The proposed implementation scheme is generic in terms of the number of FFT point, the size of memory and the size of register file in DRRA. Two implementations (DRRA-1 and DRRA-2) have been synthesized in 65 nm technology and energy/delay numbers measured with post-layout annotated gate level simulations. The results are compared to other Coarse Grain Reconfigurable Architectures (CGRAs), and dedicated FFT processors for 1024 and 2048 point FFT. For 1024 point FFT, in terms of FFT operations per unit energy, DRRA-1 and DRRA-2 outperforms all CGRA by at least 2x and is worse than ASIC by 3.45x. However, in terms of energy-delay product DRRA-2 outperforms CGRAs by at least 1.66x and dedicated FFT processors by at least 10.9x. For 2048-point FFT, DRRA-1 and DRRA-2 are 10x better for energy efficiency and 94.84 better for energy-delay product. However, radix-2 implementation is worse by 9.64x and 255x in terms of energy efficiency and energy-delay product when compared against a radix-2(4) implementation.

Place, publisher, year, edition, pages
SPRINGER , 2019. Vol. 91, no 5, p. 459-473
Keywords [en]
FFT, DRRA, CGRA, Distributed processing, 2048-point FFT, 1024-point FFT, ASIC, Dedicated processors, Synthesis, Address generation
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-252621DOI: 10.1007/s11265-017-1326-7ISI: 000467551000005Scopus ID: 2-s2.0-85065474455OAI: oai:DiVA.org:kth-252621DiVA, id: diva2:1319611
Note

QC 20190603

Available from: 2019-06-03 Created: 2019-06-03 Last updated: 2019-06-03Bibliographically approved

Open Access in DiVA

No full text in DiVA

Other links

Publisher's full textScopus

Authority records BETA

Hemani, Ahmed

Search in DiVA

By author/editor
Tajammul, Muhammad AdeelHemani, Ahmed
By organisation
School of Information and Communication Technology (ICT)
In the same journal
Journal of Signal Processing Systems
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 6 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf