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First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems. KTH.
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2018 (English)In: IEEE transactions on computer, ISSN 0018-9340, Vol. 67, no 10, p. 1430-1444Article in journal (Refereed) Published
Abstract [en]

3D integration opens up new opportunities for future multiprocessor chips by enabling fast and highly scalable 3DNetwork-on-Chip (NoC) topologies. However, in an aim to reduce the cost of Through-silicon via (TSV), partially vertically connectedNoCs, in which only a few vertical TSV links are available, have been gaining relevance. To reliably route packets under suchconditions, we introduce a lightweight, efficient and highly resilient adaptive routing algorithm targeting partially vertically connected3D-NoCs named First-Last. It requires a very low number of virtual channels (VCs) to achieve deadlock-freedom (2 VCs in the Eastand North directions and 1 VC in all other directions), and guarantees packet delivery as long as one healthy TSV connecting all layersis available anywhere in the network. An improved version of our algorithm, named Enhanced-First-Last is also introduced and shownto dramatically improve performance under low TSV availability while still using less virtual channels than state-of-the-art algorithms. Acomprehensive evaluation of the cost and performance of our algorithms is performed to demonstrate their merits with respects toexisting solutions.

Place, publisher, year, edition, pages
2018. Vol. 67, no 10, p. 1430-1444
Keywords [en]
network routing;network-on-chip;three-dimensional integrated circuits;virtual channels;healthy TSV;low TSV availability;packet delivery;3D Network-on-Chip;Enhanced-First-Last;TSV-based three-dimensional networks-on-chip;3D integration;through-silicon via;partially vertically connected 3D-NoCs;highly resilient adaptive routing algorithm;vertical TSV links;future multiprocessor chips;cost-effective adaptive routing solution;Routing;Through-silicon vias;Elevators;System recovery;Topology;Three-dimensional displays;Two dimensional displays;Network-on-Chip;3D NoC;3D integration;adaptive routing;TSV
National Category
Embedded Systems Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-254861DOI: 10.1109/TC.2018.2822269ISI: 000444003700005Scopus ID: 2-s2.0-85045190982OAI: oai:DiVA.org:kth-254861DiVA, id: diva2:1335675
Note

QC 20190813

Available from: 2019-07-05 Created: 2019-07-05 Last updated: 2019-08-13Bibliographically approved

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Ebrahimi, Masoumeh

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Citation style
  • apa
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More languages
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