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Four-level forms for memristive material implication logic
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
2019 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 27, no 5, p. 1228-1232, article id 8621037Article in journal (Refereed) Published
Abstract [en]

This brief proposes the use of four-level forms in the memristive material implication (M-IMP) logic. M-IMP is a promising approach to perform stateful logic in memristive nonvolatile memories. In such a design technique, a given Boolean function is evaluated as a sequence of instructions, making logic synthesis methods necessary to attain the shortest sequence. In comparison to previous work, experimental results have shown an average reduction of 40% when evaluating the tradeoff between the numbers of instructions and memristive devices.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc. , 2019. Vol. 27, no 5, p. 1228-1232, article id 8621037
Keywords [en]
Digital circuit design, Logic synthesis, Material implication (imp) logic, Memristor, Stateful logic, Boolean functions, Codes (symbols), Logic design, Memristors, Design technique, Non-volatile memory, Synthesis method, Computer circuits
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-252491DOI: 10.1109/TVLSI.2019.2890843Scopus ID: 2-s2.0-85065087071OAI: oai:DiVA.org:kth-252491DiVA, id: diva2:1337145
Note

QC 20190711

Available from: 2019-07-11 Created: 2019-07-11 Last updated: 2019-07-11Bibliographically approved

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Marranghello, Felipe

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