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Techniques to Reduce Folding of Noise and Interferers in PLL Charge-Pump
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2008 (English)In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008: St. Julian's; 31 August 2008 through 3 September 2008, 2008Conference paper, Published paper (Refereed)
Abstract [en]

Due to its strongly non-linear operation, charge-pump Phase Locked Loops (PLL) suffer from folding of noise and interferers. Analysis and methods reducing this effect are scarce. We analyze and propose firstly band-limiting the charge pump currents and secondly carefully selecting the minimum phase detector pulse width to eliminate specific interferers. A PLL has also been measured confirming the predicted results. Measured improvements are typically 5 dB and 20 dB for the two methods, respectively.

Place, publisher, year, edition, pages
2008.
Keyword [en]
Antenna phased arrays; Electric charge; Pumps; Charge pump currents; Linear operations; Minimum phase
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-8287DOI: 10.1109/ICECS.2008.4675041Scopus ID: 2-s2.0-57849164217ISBN: 978-1-4244-2181-7 (print)OAI: oai:DiVA.org:kth-8287DiVA: diva2:13567
Note
QC 20100817. Uppdaterad från manuskript till konferensbidrag (20100817).Available from: 2008-04-25 Created: 2008-04-25 Last updated: 2010-08-17Bibliographically approved
In thesis
1. Design and Calibration of integrated PLL Frequency Synthesizers
Open this publication in new window or tab >>Design and Calibration of integrated PLL Frequency Synthesizers
2008 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

Thanks to its ability to generate a stable yet programmable output frequency, Phase Locked Loop (PLL) frequency synthesizers are found in most modern radio transceivers. All practical PLL implementations suffer from unwanted frequency components such as phasenoise and spurious tones, and since these components affect system performance they must be predicted and minimized.

This thesis discuss the design and implementation of fully integrated PLL circuits. Techniques to predict system performance are investigated. The strongly non-linear operation of PLL building blocks are analyzed, using both analytical and numerical methods. Techniques to reduce impact of interferer down-conversion and noise folding are suggested. Methods to perform automatic calibration in order to make circuits less sensitive to process variations are proposed. The techniques are verified through a number of PLL implementations.

The design and implementation of a transceiver targeting a dual band IEEE 802.11 a/b/g wireless LAN operation is discussed. The circuit use two PLL:s operating at 1310 to 1510 MHz and 3.84 GHz respectively. Noise contributions of various PLL building blocks and their impact on over all system performance are analyzed. The combined integrated phase noise is below -34 dBc, and measured transceiver Error Vector Magnitude (EVM) is better than 2.5 dB in both the 2.4 and 5 GHz bands.

A low power frequency synthesizer targeting Frequency Shift Keying applications such as ZigBee and BlueTooth is presented. The synthesizer use open-loop direct modulation of the carrier, but unlike conventional implementations, the proposed synthesizer is open both when transmitting and receiving data. This allows the use of a small area on-chip loop filter without violating noise or spurious requirements. To handle the frequency drift normally associated with open-loop implementations, a low-leakage charge-pump is proposed. The synthesizer is implemented using a 0.18μm CMOS process. Total power consumption is 9 mW and the circuit area including the VCO inductors and on-chip loopfilter is 0.32mm2. Measured leakage current is less than 2 fA.

A small area amplitude detector circuit is proposed. The wide-band operation and small input capacitance make the circuit suitable for embedding in an RF system on-chip, allowing measurement of on-chip signal levels and automatic calibration.

Finally an oscillator topology reducing the phase noise in voltage controlled oscillators is suggested. By using on-chip decoupling and an amplitude control circuit to adjust oscillator bias, the impact of current source noise is eliminated. The theoretical phase noise is reduced 3.9 dB compared to a conventional LC oscillator using the same bias current.

Place, publisher, year, edition, pages
Stockholm: KTH, 2008. xv, 141 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 08:03
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-4711 (URN)
Public defence
2008-04-28, Sal D, KTH-Forum, Isafjordsgatan 39, Kista, 13:15
Opponent
Supervisors
Note
QC 20100817Available from: 2008-04-25 Created: 2008-04-25 Last updated: 2010-08-17Bibliographically approved

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