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A Current Shaping Technique to Lower Phase Noise in LC Oscillators
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
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2008 (English)In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008: St. Julian's; 31 August 2008 through 3 September 2008, 2008, 392-395 p.Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
2008. 392-395 p.
Keyword [en]
Oscillators (electronic); Phase noise; Tanks (containers); Active devices; Bias noises; Closed forms; LC oscillators; Lc tanks; Noise equations; Phase noise performances; Shaping techniques
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-8289DOI: 10.1109/ICECS.2008.4674873Scopus ID: 2-s2.0-57849164229OAI: oai:DiVA.org:kth-8289DiVA: diva2:13569
Conference
IEEE ICECS 2008
Note

QC 20100817

Available from: 2008-04-25 Created: 2008-04-25 Last updated: 2016-04-27Bibliographically approved
In thesis
1. Design and Calibration of integrated PLL Frequency Synthesizers
Open this publication in new window or tab >>Design and Calibration of integrated PLL Frequency Synthesizers
2008 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

Thanks to its ability to generate a stable yet programmable output frequency, Phase Locked Loop (PLL) frequency synthesizers are found in most modern radio transceivers. All practical PLL implementations suffer from unwanted frequency components such as phasenoise and spurious tones, and since these components affect system performance they must be predicted and minimized.

This thesis discuss the design and implementation of fully integrated PLL circuits. Techniques to predict system performance are investigated. The strongly non-linear operation of PLL building blocks are analyzed, using both analytical and numerical methods. Techniques to reduce impact of interferer down-conversion and noise folding are suggested. Methods to perform automatic calibration in order to make circuits less sensitive to process variations are proposed. The techniques are verified through a number of PLL implementations.

The design and implementation of a transceiver targeting a dual band IEEE 802.11 a/b/g wireless LAN operation is discussed. The circuit use two PLL:s operating at 1310 to 1510 MHz and 3.84 GHz respectively. Noise contributions of various PLL building blocks and their impact on over all system performance are analyzed. The combined integrated phase noise is below -34 dBc, and measured transceiver Error Vector Magnitude (EVM) is better than 2.5 dB in both the 2.4 and 5 GHz bands.

A low power frequency synthesizer targeting Frequency Shift Keying applications such as ZigBee and BlueTooth is presented. The synthesizer use open-loop direct modulation of the carrier, but unlike conventional implementations, the proposed synthesizer is open both when transmitting and receiving data. This allows the use of a small area on-chip loop filter without violating noise or spurious requirements. To handle the frequency drift normally associated with open-loop implementations, a low-leakage charge-pump is proposed. The synthesizer is implemented using a 0.18μm CMOS process. Total power consumption is 9 mW and the circuit area including the VCO inductors and on-chip loopfilter is 0.32mm2. Measured leakage current is less than 2 fA.

A small area amplitude detector circuit is proposed. The wide-band operation and small input capacitance make the circuit suitable for embedding in an RF system on-chip, allowing measurement of on-chip signal levels and automatic calibration.

Finally an oscillator topology reducing the phase noise in voltage controlled oscillators is suggested. By using on-chip decoupling and an amplitude control circuit to adjust oscillator bias, the impact of current source noise is eliminated. The theoretical phase noise is reduced 3.9 dB compared to a conventional LC oscillator using the same bias current.

Place, publisher, year, edition, pages
Stockholm: KTH, 2008. xv, 141 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 08:03
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-4711 (URN)
Public defence
2008-04-28, Sal D, KTH-Forum, Isafjordsgatan 39, Kista, 13:15
Opponent
Supervisors
Note
QC 20100817Available from: 2008-04-25 Created: 2008-04-25 Last updated: 2010-08-17Bibliographically approved
2. Low Noise Oscillator in ADPLL toward Direct-to-RF All-digital Polar Transmitter
Open this publication in new window or tab >>Low Noise Oscillator in ADPLL toward Direct-to-RF All-digital Polar Transmitter
2012 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In recent years all-digital or digitally-intensive RF transmitters (TX) have attracted great attention in both literature and industry. The motivation is to implement RF circuits in a manner suiting advanced nanometer CMOS processes. To achieve that, information is encoded in the time-domain rather than voltage amplitude. This enables RF design to also benefit from CMOS process scaling. In this thesis an improved architecture of a digitally-intensive transmitter is proposed and validated experimentally. The techniques to lower oscillator phase noise and all-digital phase-locked loop (ADPLL) quantization noise are discussed and proved by both simulation and measurements.

The impact of device sizing on 1/f^2 phase noise is analyzed and validated by measurements. Seven oscillators in 180-nm CMOS with the same LC-tank, operation frequency and power consumption but different core device width are compared. The conclusion clarify the different suggestions on device sizing in the literature. It is illustrated that tail noise contribution is strongly positive dependent to core device sizing, while the contribution of core devices themselves is weakly dependent. Measurements demonstrate that there is a 14-dB phase noise increase when sizing core devices from 40 um to 280 um in the case of noisy tail current. If tail current is clean, the increase is only 4 dB.  For 1/f^3 phase noise, the investigation reveals that the capacitance modulation is the dominant factor accounting for the 1/f or flick noise up-conversion, which is proved by measurements of 180-nm CMOS designs.   A class-C oscillator with ensured start-up and constant amplitude is presented. It achieves a 3.9-dB phase noise reduction in theory and 5-dB reduction in measurements, compared to a conventional LC-tank oscillator operating at the same frequency and power. With the help of a digital bias voltage and bias current control loop, a 191 Figure-of-Merit (FoM) is achieved, showing the ability for low power and noise application.   The previous oscillator optimization techniques have been applied in designing a digital controlled oscillator (DCO) for an ADPLL. A fine tuning varactor is proposed to reduce quantization noise, achieving a frequency step of only several hundreds Hz. In order to measure this small frequency step when the DCO is free-running, a method based on the narrow-band frequency modulation (FM) theory is proposed. The ADPLL wide-band FM is fulfilled by using a digital two-point modulation so that the modulation bandwidth is not limited by the ADPLL loop dynamic.

Finally an all-digital polar TX is proposed based on an improved architecture. The ADPLL is used for FM while a one-bit low-pass Sigma Delta modulator using the phase modulated ADPLL output as the clock accomplishes amplitude modulation. A simple AND gate is adopted to increase the fundamental power as mixers. A class-D power amplifier stages diliver 6.8-dBm power to antenna through a on-chip band-pass pre-filter. The filter also acts as single-ended to differential-end conversion and matching network.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2012. xi, 97 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 13:03
Keyword
all-digital, digitally-intensive, frequency modualtion, phase modulation, amplitude modulation, polar, transmitter, oscillator, digital controled oscillator, DCO, VCO, voltage controled oscillator, class-C oscillator, class-D PA, ADPLL, phase noise, RF, CMOS.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-118818 (URN)978-91-7501-643-6 (ISBN)
Public defence
2013-03-13, Sal D, KTH-Forum, Isafjordsgatan 39, Kista, 09:00 (English)
Opponent
Supervisors
Available from: 2013-02-28 Created: 2013-02-28 Last updated: 2013-02-28Bibliographically approved

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Chen, JianJonsson, FredrikOlsson, HåkanZheng, Li-Rong
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