Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Design and Calibration of integrated PLL Frequency Synthesizers
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2008 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

Thanks to its ability to generate a stable yet programmable output frequency, Phase Locked Loop (PLL) frequency synthesizers are found in most modern radio transceivers. All practical PLL implementations suffer from unwanted frequency components such as phasenoise and spurious tones, and since these components affect system performance they must be predicted and minimized.

This thesis discuss the design and implementation of fully integrated PLL circuits. Techniques to predict system performance are investigated. The strongly non-linear operation of PLL building blocks are analyzed, using both analytical and numerical methods. Techniques to reduce impact of interferer down-conversion and noise folding are suggested. Methods to perform automatic calibration in order to make circuits less sensitive to process variations are proposed. The techniques are verified through a number of PLL implementations.

The design and implementation of a transceiver targeting a dual band IEEE 802.11 a/b/g wireless LAN operation is discussed. The circuit use two PLL:s operating at 1310 to 1510 MHz and 3.84 GHz respectively. Noise contributions of various PLL building blocks and their impact on over all system performance are analyzed. The combined integrated phase noise is below -34 dBc, and measured transceiver Error Vector Magnitude (EVM) is better than 2.5 dB in both the 2.4 and 5 GHz bands.

A low power frequency synthesizer targeting Frequency Shift Keying applications such as ZigBee and BlueTooth is presented. The synthesizer use open-loop direct modulation of the carrier, but unlike conventional implementations, the proposed synthesizer is open both when transmitting and receiving data. This allows the use of a small area on-chip loop filter without violating noise or spurious requirements. To handle the frequency drift normally associated with open-loop implementations, a low-leakage charge-pump is proposed. The synthesizer is implemented using a 0.18μm CMOS process. Total power consumption is 9 mW and the circuit area including the VCO inductors and on-chip loopfilter is 0.32mm2. Measured leakage current is less than 2 fA.

A small area amplitude detector circuit is proposed. The wide-band operation and small input capacitance make the circuit suitable for embedding in an RF system on-chip, allowing measurement of on-chip signal levels and automatic calibration.

Finally an oscillator topology reducing the phase noise in voltage controlled oscillators is suggested. By using on-chip decoupling and an amplitude control circuit to adjust oscillator bias, the impact of current source noise is eliminated. The theoretical phase noise is reduced 3.9 dB compared to a conventional LC oscillator using the same bias current.

Place, publisher, year, edition, pages
Stockholm: KTH , 2008. , xv, 141 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 08:03
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-4711OAI: oai:DiVA.org:kth-4711DiVA: diva2:13570
Public defence
2008-04-28, Sal D, KTH-Forum, Isafjordsgatan 39, Kista, 13:15
Opponent
Supervisors
Note
QC 20100817Available from: 2008-04-25 Created: 2008-04-25 Last updated: 2010-08-17Bibliographically approved
List of papers
1. A low-leakage open-loop frequency synthesizer allowing small-area on-chip loop filter
Open this publication in new window or tab >>A low-leakage open-loop frequency synthesizer allowing small-area on-chip loop filter
2009 (English)In: IEEE Transactions on Circuits and Systems II: Express Briefs, ISSN 1549-7747, Vol. 56, no 3, 195-199 p.Article in journal (Refereed) Published
Abstract [en]

A frequency synthesizer targeting low-power packet-based frequency-shift-keying (FSK) applications using open-loop modulation of the oscillator is presented. Unlike conventional implementations, the proposed synthesizer is open both when transmitting and receiving data. It is, therefore, possible to use a wide loop-filter bandwidth without violating the noise or spurious requirements. A wideband loop-filter can be implemented using small component values, allowing an on-chip loop filter. To handle the frequency drift associated with open-loop implementations, a low-leakage charge pump is proposed. The synthesizer is implemented using a 0.18-mu m CMOS process. The total power consumption is 9 mW, and the circuit area including the voltage-controlled oscillator (VCO) inductors and on-chip loop-filter is 0.32 mm(2). The measured frequency drift indicates a leakage current of below 2 fA.

Keyword
Frequency modulation; frequency stability; frequency synthesizers; leakage currents; phase locked loops; phase noise; transceivers
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-8281 (URN)10.1109/TCSII.2009.2015366 (DOI)000264628900003 ()2-s2.0-64049106123 (Scopus ID)
Note
QC 20100816. Uppdaterad från manuskript till artikel (20100816).Available from: 2008-04-25 Created: 2008-04-25 Last updated: 2010-08-17Bibliographically approved
2. RF detector for on-chip amplitude measurements
Open this publication in new window or tab >>RF detector for on-chip amplitude measurements
2004 (English)In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 40, no 20, 1239-1241 p.Article in journal (Refereed) Published
Abstract [en]

A novel on-chip amplitude detector that allows for efficient debugging of complex RF circuits is proposed. The simplicity, low power consumption, flat frequency response, minimal loading of the tested circuit and possibility of multiplexing makes this detector suitable for on-chip RF amplitude measurements. Simulations and measurements confirm the detector operation.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-8282 (URN)10.1049/el:20045841 (DOI)000224346300003 ()2-s2.0-6444240784 (Scopus ID)
Note
QC 20100816 Available from: 2008-04-25 Created: 2008-04-25 Last updated: 2017-12-14Bibliographically approved
3. A quadrature oscillator using simplified phase and amplitude calibration
Open this publication in new window or tab >>A quadrature oscillator using simplified phase and amplitude calibration
2008 (English)In: 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008: Seattle, WA; 18 May 2008 through 21 May 2008, 2008, 992-995 p.Conference paper, Published paper (Refereed)
Abstract [en]

A quadrature oscillator using automatic calibration of phase and amplitude is presented. It is shown that phase errors in a quadrature oscillator will create an amplitude difference between the outputs. The proposed calibration scheme use on-chip amplitude detectors connected in a negative feedback loop to detect and compensate these amplitude differences. The calibration scheme can be implemented using small chip area and low current consumption compared to other calibration schemes. A quadrature oscillator using the proposed calibration is simulated using a 0.18 mu m CMOS process to verify the feasibility of the proposed method.

Series
IEEE INTERNATIONAL SYMP ON CIRCUITS AND SYSTEMS, ISSN 0277-674X
Keyword
NOISE; VCO; International symposium; Quadrature oscillators
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-24130 (URN)10.1109/ISCAS.2008.4541587 (DOI)000258532100252 ()2-s2.0-51749112467 (Scopus ID)978-1-4244-2078-0 (ISBN)
Note
QC 20100816. Tidigare titel: A Quadrature Oscillator using automatic phase and amplitude tuningAvailable from: 2010-08-16 Created: 2010-08-16 Last updated: 2010-08-16Bibliographically approved
4. A single-chip CMOS transceiver for 802.11a/b/g wireless LANs
Open this publication in new window or tab >>A single-chip CMOS transceiver for 802.11a/b/g wireless LANs
2004 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 39, no 12, 2250-2258 p.Article in journal (Refereed) Published
Abstract [en]

A dual-band trimode radio fully compliant with the IEEE 802.11a, b, and g standards is implemented in a 0.18-mum CMOS process and packaged in a 48-pin QFN package. The transceiver achieves a receiver noise figure of 4.9/5.6 dB for the 2.4-GHz/5-GHz bands, respectively, and a transmit error vector magnitude (EVM) of 2.5% for both bands. The transmit output power is digitally controlled, allowing per-packet power control as required by the forthcoming 802.11 h standard. A quadrature accuracy of 0.3degrees in phase and 0.05 dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a total integrated phase noise of better than -34 dBc. Compatibility with multiple baseband chips is ensured by flexible interfaces toward the A/D and D/A converters, as well as a calibration scheme not requiring any baseband support. The chip passes +/-2 kV human body model ESD testing on all pins, including the RF pins. The total die area is 12 mm(2). The power consumption is 207 mW in the receive mode and 247 mW in the transmit mode using a 1.8-V supply.

Keyword
dual conversion; IEEE 802.11a/b/g; orthogonal frequency-division multiplexing (OFDM); receiver; RF CMOS; RF transceiver; synthesizer; transmitter; wireless LAN (WLAN)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-8284 (URN)10.1109/JSSC.2004.836334 (DOI)000225363900016 ()
Note
QC 20100816Available from: 2008-04-25 Created: 2008-04-25 Last updated: 2017-12-14Bibliographically approved
5. A Single Chip 802.11 a/b/g WLAN Transceiver
Open this publication in new window or tab >>A Single Chip 802.11 a/b/g WLAN Transceiver
2004 (English)In: 22nd Norchip Conference: Oslo; 8 November 2004 through 9 November 2004, 2004, 233-236 p.Conference paper, Published paper (Refereed)
Abstract [en]

A dual-band triple mode radio compliant with the IEEE 802.11 a/b/g standard implemented in a 0.18 μm CMOS process is presented. The transceiver is compatible with a large number of basebands due to its flexible interface towards AD / DA converters and on-chip automatic calibration of on-chip filters and oscillators. The transceiver achieves a receiver noise figure of 4.9/5.6dB for the 2.4GHz/5GHz bands, respectively, and a minimum transmit error vector magnitude (EVM) of 2.5% for both bands. A quadrature accuracy of 0.3° in phase and 0.05dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a better than -34dBc total integrated phase noise. The chip passes ±2kV human body model ESD testing on all pins, including the RF pins. The total die area is 12mm2. The power consumption is 207mW in the receive mode and 247mW in the transmit mode using a 1.8V supply.

Keyword
Bandpass filters; CMOS integrated circuits; Local area networks; Microprocessor chips; Natural frequencies; Networks (circuits); Orthogonal frequency division multiplexing; Oscillators (electronic); Basebands; Error vector magnitude; Radio transceivers; Wireless local area networks (WLAN)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-8285 (URN)10.1109/NORCHP.2004.1423866 (DOI)000227801500058 ()0-7803-8510-1 (ISBN)
Note
QC 20100816Available from: 2008-04-25 Created: 2008-04-25 Last updated: 2010-08-17Bibliographically approved
6. Folding of Noise and Interferers in PLL Charge-Pumps
Open this publication in new window or tab >>Folding of Noise and Interferers in PLL Charge-Pumps
2007 (English)Article in journal (Other academic) Submitted
Keyword
Phase locked loops, phase noise, Interference supression, Charge pumps
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-8286 (URN)
Note
QS 20120316Available from: 2008-04-25 Created: 2008-04-25 Last updated: 2012-03-16Bibliographically approved
7. Techniques to Reduce Folding of Noise and Interferers in PLL Charge-Pump
Open this publication in new window or tab >>Techniques to Reduce Folding of Noise and Interferers in PLL Charge-Pump
2008 (English)In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008: St. Julian's; 31 August 2008 through 3 September 2008, 2008Conference paper, Published paper (Refereed)
Abstract [en]

Due to its strongly non-linear operation, charge-pump Phase Locked Loops (PLL) suffer from folding of noise and interferers. Analysis and methods reducing this effect are scarce. We analyze and propose firstly band-limiting the charge pump currents and secondly carefully selecting the minimum phase detector pulse width to eliminate specific interferers. A PLL has also been measured confirming the predicted results. Measured improvements are typically 5 dB and 20 dB for the two methods, respectively.

Keyword
Antenna phased arrays; Electric charge; Pumps; Charge pump currents; Linear operations; Minimum phase
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-8287 (URN)10.1109/ICECS.2008.4675041 (DOI)2-s2.0-57849164217 (Scopus ID)978-1-4244-2181-7 (ISBN)
Note
QC 20100817. Uppdaterad från manuskript till konferensbidrag (20100817).Available from: 2008-04-25 Created: 2008-04-25 Last updated: 2010-08-17Bibliographically approved
8. A Voltage Controlled Oscillator with Automatic Amplitude Control in SiGe Technology
Open this publication in new window or tab >>A Voltage Controlled Oscillator with Automatic Amplitude Control in SiGe Technology
Show others...
2001 (English)In: 19th Norchip: Kista 12-13 November 2001, 2001, 28-33 p.Conference paper, Published paper (Refereed)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-8288 (URN)
Note
QC 20100817Available from: 2008-04-25 Created: 2008-04-25 Last updated: 2010-08-17Bibliographically approved
9. A Current Shaping Technique to Lower Phase Noise in LC Oscillators
Open this publication in new window or tab >>A Current Shaping Technique to Lower Phase Noise in LC Oscillators
Show others...
2008 (English)In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008: St. Julian's; 31 August 2008 through 3 September 2008, 2008, 392-395 p.Conference paper, Published paper (Refereed)
Keyword
Oscillators (electronic); Phase noise; Tanks (containers); Active devices; Bias noises; Closed forms; LC oscillators; Lc tanks; Noise equations; Phase noise performances; Shaping techniques
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-8289 (URN)10.1109/ICECS.2008.4674873 (DOI)2-s2.0-57849164229 (Scopus ID)
Conference
IEEE ICECS 2008
Note

QC 20100817

Available from: 2008-04-25 Created: 2008-04-25 Last updated: 2016-04-27Bibliographically approved

Open Access in DiVA

fulltext(5186 kB)16110 downloads
File information
File name FULLTEXT01.pdfFile size 5186 kBChecksum MD5
20575b7cfdb702a81617a017531470b84087b39896deafb5052570a05860dbb609e19193
Type fulltextMimetype application/pdf

Search in DiVA

By author/editor
Jonsson, Fredrik
By organisation
Electronic, Computer and Software Systems, ECS
Other Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar
Total: 16110 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

urn-nbn

Altmetric score

urn-nbn
Total: 1580 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf