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Cost and performance tradeoff analysis in radio and mixed-signal system-on-package design
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
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2004 (English)In: IEEE Transactions on Advanced Packaging, ISSN 1521-3323, E-ISSN 1557-9980, Vol. 27, no 2, 364-375 p.Article in journal (Refereed) Published
Abstract [en]

An optimal total solution for radio and mixed-signal system integration needs tradeoffs between different design options. Among various design metrics, cost and performance are probably the two most important factors for design decisions. In this paper, we review and analyze cost-performance tradeoffs of system-on-chip (SOC) versus system-on-Package (SOP) solutions for radio and mixed-signal applications. A new design methodology, which quantitatively predicts performance and cost gains of SOP versus SOC,is presented. The performance model evaluates various mixed-signal isolation techniques between sensitive analog/RF circuits and noisy digital circuits in SOC or SOP. The cost analysis includes new factors such as extra chip area and additional process steps for mixed-signal isolation, seamless integration of "virtual components" or intellectual property (IP) modules, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, and extra costs for moving passives off chip. In addition to these, a complete and systematic analysis method for on-chip versus off-chip passives tradeoffs is presented. The analysis and modeling techniques explore tradeoffs between performance, cost, robustness, and yield when different on-chip or off-chip passives are used. It thus provides a complete picture of quantitative tradeoffs for using on-chip or off-chip passives. The design methodology and analysis techniques are then demonstrated through several design examples in wireless applications. It is clearly shown that for all complex and high performance mixed-signal systems, SOP is a lower cost solution than SOC. Finally,some design guidelines for SOC versus SOP and on-chip versus off-chip are concluded.

Place, publisher, year, edition, pages
2004. Vol. 27, no 2, 364-375 p.
Keyword [en]
cost modelling, mixed-signal systems, performance estimation, radio electronics, system-on-chip (SOC), system-on-package (SOP)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-8471DOI: 10.1109/TADVP.2004.828818ISI: 000223599100014Scopus ID: 2-s2.0-4544375231OAI: oai:DiVA.org:kth-8471DiVA: diva2:13804
Note
QC 20100907Available from: 2005-11-03 Created: 2005-11-03 Last updated: 2017-12-14Bibliographically approved
In thesis
1. Concurrent chip and package design for radio and mixed-signal systems
Open this publication in new window or tab >>Concurrent chip and package design for radio and mixed-signal systems
2005 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

The advances in VLSI and packaging technologies enable us to integrate a whole system on a single chip (SoC) or on a package module. In these systems, analog/RF electronics, digital circuitries, and memories coexist. This new technology brings us new freedom for system integration as well as new challenges in system design and implementation. To fully utilize the benefits of these new hardware technologies, concurrent design of system, chip, and package is necessary. This research aims to explore the new design space and opportunities for System-on-Package (SoP), with special attention on radio and mixed-signal system applications. Global level system partitioning for SoC and SoP with cost-performance trade-off, concurrent chip and design for high-speed off-chip signaling, global clock distribution, and ultra wideband (UWB) radio module are two fields in this research.

Cost-performance driven for mixed-signal system partitioning in early conceptual level design is first addressed in this thesis. We develop a modeling technique to pre-estimate the cost and performance. The performance model evaluates various noise isolation technologies, such as using guard rings, and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or “virtual components”, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip are considered. An efficient computation algorithm, namely COMSI, is developed for cost estimation under various mixed-signal performance constraints.

System interconnect topologies have been moving away from multi-point bus architecture and towards high-speed serial links. But low interaction between chip and package design has more and more limited system performance. We address concurrent chip and package design and co-optimization for high-speed off-chip signaling in this part. First we explore the interconnect and package constraints to the circuit and system architecture. Proper equivalent circuit models for package parasitics are set up and then a 3-dimension electromagnetic (EM) solver is used to extract the parasitic parameters of package. After that, bandwidth and noise of the signal channel are estimated. The optimal off-chip singling is designed according to these packages and interconnection constraints. We also analyzed the global clock distribution using co-design method.

We developed a low cost, low power consumption, and low complexity UWB radio module using co-design method and SoP technologies. The module will be used in low data rate and long-range wireless intelligent systems such as radio frequency identification (RFID) or wireless sensors networks (WSN). Liquid-crystal-polymer (LCP) based SoP technologies were used to implement the module.

Place, publisher, year, edition, pages
Stockholm: KTH, 2005. xi, 55 p.
Series
Trita-IMIT. LECS, ISSN 1651-4076 ; 05:09
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-476 (URN)91-7178-181-7 (ISBN)
Public defence
2005-11-24, Sal D, KTH-Forum, Isafjordsgatan 39, Kista, 13:15
Opponent
Supervisors
Note

QC 20101006

Available from: 2005-11-03 Created: 2005-11-03 Last updated: 2012-10-03Bibliographically approved
2. System-on-package solutions for multi-band RF front end
Open this publication in new window or tab >>System-on-package solutions for multi-band RF front end
2005 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

Advances in microelectronics technology have enabled us to integrate a complex electronic system (such as a radio) on a single chip or in a single package module, known as system-on-chip (SoC) and system-on-package (SoP) paradigms. This brings not only new opportunities for system integration, but also challenges in design and implementation. One of these challenges is how to achieve an optimum total solution of system integration via chip and package co-design, because there is no tool or design methodology available for such kind of optimization. This thesis focuses on innovative multi-band multi-standard radio front-end design and explores a new design methodology. The motivation of developing this design methodology is to achieve an optimum total solution for radio system implementation via chip and package co-design and co-optimization.

The methodology starts from RF packaging and components modeling. Necessary models for both on-chip and off-chip passives are developed. Parasitic effects of packages for radio chips are modeled for particular frequencies. Compared with high-speed digital packaging, RF packaging normally deals with narrow band signals. It is possible to absorb some unwanted parasitics by designing proper port matching networks. In addition, cost-performance trade-offs are performed. In this context, we first developed process and technology based cost models, which include parameters like chip real estate, raw materials, package, test and rework. Impact of process variation on final yield has also been considered in the models by using a statistical analysis approach. Performance of different design options is measured by a special FoM (figure-of-merit). Each type of analog/RF circuit (such as LNA, PA and ADC) has its own dedicated FoM. Through a series of cost-performance trade-offs for different on-chip versus off-chip passives and partitions, an optimum total solution is obtained.

Finally, this methodology was demonstrated via a number of design examples for multi-band multi-standard radio front-end. The author has explored the optimum solutions for different circuit architectures and process technologies encompassing parallel, concurrent and digitally programmable multi-band radio frond-end blocks. It is interesting to find that, for complex RF circuits like a multi-band multi-standard radio, moving some passives off-chip will have significant cost-savings. In addition to the above contributions, the author has also developed an MCM-D technology on LCP and glass substrates, based on metal deposition and BCB spin-coating at KTH clean room. The author has also performed some preliminary studies on UWB radio for RFID applications.

Place, publisher, year, edition, pages
Stockholm: KTH, 2005. ix, 88 p.
Series
Trita-IMIT. LECS, ISSN 1651-4076 ; 2005:08
Keyword
chip-package co-design, multi-band radio, system-on-package
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-482 (URN)91-7178-187-0 (ISBN)
Public defence
2005-11-25, Sal D, KTH-Forum, 10:00
Opponent
Supervisors
Note
QC 20101005Available from: 2005-11-09 Created: 2005-11-09 Last updated: 2010-10-05Bibliographically approved

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