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Robustness enhancement through chip-package co-design for high-speed electronics
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
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2005 (English)In: Microelectronics Journal, ISSN 0959-8324, Vol. 36, no 9, 846-855 p.Article in journal (Refereed) Published
Abstract [en]

The low interaction between chip and package design has an increasingly limiting effect on the system performance. In this paper, the chip-package co-design flow is presented. We address robustness enhancement under the package and interconnection constraints as well as process, voltage, and temperature (PVT) variations by using impedance control, optimal pins assignment and transmitter equalization. From the simulation results we find that without on-chip digital compensation circuit, the variation of the driver's output impedance is 37% under different PVT conditions. However, it is only 5% when digital compensation circuit is used. Through optimal pins assignment the effective inductance of the pins is reduced. When power and ground pins are used as shielding pins, crosstalk is also decreased by 10 dB. Transmitter equalization effectively decreases inter-symbol interference caused by interconnection attenuation and dispersion. In our design example we find that without equalization the eye-diagram is almost closed at the receiver end. On the other hand with one-tap pre-emphasis equalization the eye-diagram is open and has a height of 90 mV and a width of 140 ps. It is also found that there is a clear optimal window for high data rate in this design. Without a chip-package co-design such an optimal window will not be found.

Place, publisher, year, edition, pages
2005. Vol. 36, no 9, 846-855 p.
Keyword [en]
chip-package co-design, pins assignment, impedance-controlled package, equalization
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-8473DOI: 10.1016/j.mejo.2005.03.007ISI: 000231592000007Scopus ID: 2-s2.0-23844536828OAI: oai:DiVA.org:kth-8473DiVA: diva2:13806
Note

QC 20100928

Available from: 2005-11-03 Created: 2005-11-03 Last updated: 2012-09-21Bibliographically approved
In thesis
1. Concurrent chip and package design for radio and mixed-signal systems
Open this publication in new window or tab >>Concurrent chip and package design for radio and mixed-signal systems
2005 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

The advances in VLSI and packaging technologies enable us to integrate a whole system on a single chip (SoC) or on a package module. In these systems, analog/RF electronics, digital circuitries, and memories coexist. This new technology brings us new freedom for system integration as well as new challenges in system design and implementation. To fully utilize the benefits of these new hardware technologies, concurrent design of system, chip, and package is necessary. This research aims to explore the new design space and opportunities for System-on-Package (SoP), with special attention on radio and mixed-signal system applications. Global level system partitioning for SoC and SoP with cost-performance trade-off, concurrent chip and design for high-speed off-chip signaling, global clock distribution, and ultra wideband (UWB) radio module are two fields in this research.

Cost-performance driven for mixed-signal system partitioning in early conceptual level design is first addressed in this thesis. We develop a modeling technique to pre-estimate the cost and performance. The performance model evaluates various noise isolation technologies, such as using guard rings, and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or “virtual components”, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip are considered. An efficient computation algorithm, namely COMSI, is developed for cost estimation under various mixed-signal performance constraints.

System interconnect topologies have been moving away from multi-point bus architecture and towards high-speed serial links. But low interaction between chip and package design has more and more limited system performance. We address concurrent chip and package design and co-optimization for high-speed off-chip signaling in this part. First we explore the interconnect and package constraints to the circuit and system architecture. Proper equivalent circuit models for package parasitics are set up and then a 3-dimension electromagnetic (EM) solver is used to extract the parasitic parameters of package. After that, bandwidth and noise of the signal channel are estimated. The optimal off-chip singling is designed according to these packages and interconnection constraints. We also analyzed the global clock distribution using co-design method.

We developed a low cost, low power consumption, and low complexity UWB radio module using co-design method and SoP technologies. The module will be used in low data rate and long-range wireless intelligent systems such as radio frequency identification (RFID) or wireless sensors networks (WSN). Liquid-crystal-polymer (LCP) based SoP technologies were used to implement the module.

Place, publisher, year, edition, pages
Stockholm: KTH, 2005. xi, 55 p.
Series
Trita-IMIT. LECS, ISSN 1651-4076 ; 05:09
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-476 (URN)91-7178-181-7 (ISBN)
Public defence
2005-11-24, Sal D, KTH-Forum, Isafjordsgatan 39, Kista, 13:15
Opponent
Supervisors
Note

QC 20101006

Available from: 2005-11-03 Created: 2005-11-03 Last updated: 2012-10-03Bibliographically approved

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