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Concurrent chip-package design for 10GHz global clock distribution network
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
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2005 (English)In: 55th Electronic Components & Technology Conference, Vols 1 and 2, 2005 Proceedings, 2005, 1554-1559 p.Conference paper, Published paper (Refereed)
Abstract [en]

As a result of the continuous downscaling of the CMOS technology, on chip frequency for high performance microprocessor will soon arrive 10GHz according to international technology roadmap for semiconductors (ITRS). In this paper, a 10GHz global clock distribution network using standing wave approach was analyzed on chip and package level. On chip level, a 10GHz standing wave oscillator (SWO) for global clock distribution network using 0.18um, 1P6M CMOS technology, is designed and analyzed. The simulation results show that the skew is well controlled (about 1ps) while the clock frequency variation is about 20% because power/ground return paths exist in different metal layers. On package level, we assume that the chip size is 20mm*20mm and flip-chip bonding technology is used. The simulation results show that the skew at random positions of the transmission line (spiral or serpentine shape) is within 10% of tau(clk) when the attenuation is about 1.5dB. For attenuation from 1.5dB to 6.7dB, the peak positions (n*lambda/2) can be used as clock node. For the mesh and plane shape, the skew is controlled within 10% of tau(clk) using standing wave method.

Place, publisher, year, edition, pages
2005. 1554-1559 p.
Series
Proceedings - Electronic Components and Technology Conference, ISSN 0569-5503
Keyword [en]
Attenuation, Clocks, CMOS integrated circuits, Concurrent engineering, Microprocessor chips, Semiconductor device manufacture, Transmission line theory
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-8474DOI: 10.1109/ECTC.2005.1441995ISI: 000230581600243Scopus ID: 2-s2.0-24644487124ISBN: 0-7803-8906-9 (print)OAI: oai:DiVA.org:kth-8474DiVA: diva2:13807
Conference
Electronic Components and Technology Conference, 2005. Proceedings. 55th, Lake Buena Vista, Florida, USA, May 31- June 3, 2005
Note

QC 20101006

Available from: 2005-11-03 Created: 2005-11-03 Last updated: 2014-12-04Bibliographically approved
In thesis
1. Concurrent chip and package design for radio and mixed-signal systems
Open this publication in new window or tab >>Concurrent chip and package design for radio and mixed-signal systems
2005 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

The advances in VLSI and packaging technologies enable us to integrate a whole system on a single chip (SoC) or on a package module. In these systems, analog/RF electronics, digital circuitries, and memories coexist. This new technology brings us new freedom for system integration as well as new challenges in system design and implementation. To fully utilize the benefits of these new hardware technologies, concurrent design of system, chip, and package is necessary. This research aims to explore the new design space and opportunities for System-on-Package (SoP), with special attention on radio and mixed-signal system applications. Global level system partitioning for SoC and SoP with cost-performance trade-off, concurrent chip and design for high-speed off-chip signaling, global clock distribution, and ultra wideband (UWB) radio module are two fields in this research.

Cost-performance driven for mixed-signal system partitioning in early conceptual level design is first addressed in this thesis. We develop a modeling technique to pre-estimate the cost and performance. The performance model evaluates various noise isolation technologies, such as using guard rings, and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or “virtual components”, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip are considered. An efficient computation algorithm, namely COMSI, is developed for cost estimation under various mixed-signal performance constraints.

System interconnect topologies have been moving away from multi-point bus architecture and towards high-speed serial links. But low interaction between chip and package design has more and more limited system performance. We address concurrent chip and package design and co-optimization for high-speed off-chip signaling in this part. First we explore the interconnect and package constraints to the circuit and system architecture. Proper equivalent circuit models for package parasitics are set up and then a 3-dimension electromagnetic (EM) solver is used to extract the parasitic parameters of package. After that, bandwidth and noise of the signal channel are estimated. The optimal off-chip singling is designed according to these packages and interconnection constraints. We also analyzed the global clock distribution using co-design method.

We developed a low cost, low power consumption, and low complexity UWB radio module using co-design method and SoP technologies. The module will be used in low data rate and long-range wireless intelligent systems such as radio frequency identification (RFID) or wireless sensors networks (WSN). Liquid-crystal-polymer (LCP) based SoP technologies were used to implement the module.

Place, publisher, year, edition, pages
Stockholm: KTH, 2005. xi, 55 p.
Series
Trita-IMIT. LECS, ISSN 1651-4076 ; 05:09
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-476 (URN)91-7178-181-7 (ISBN)
Public defence
2005-11-24, Sal D, KTH-Forum, Isafjordsgatan 39, Kista, 13:15
Opponent
Supervisors
Note

QC 20101006

Available from: 2005-11-03 Created: 2005-11-03 Last updated: 2012-10-03Bibliographically approved

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Citation style
  • apa
  • harvard1
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  • modern-language-association-8th-edition
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Output format
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