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Concurrent chip and package design for radio and mixed-signal systems
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2005 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

The advances in VLSI and packaging technologies enable us to integrate a whole system on a single chip (SoC) or on a package module. In these systems, analog/RF electronics, digital circuitries, and memories coexist. This new technology brings us new freedom for system integration as well as new challenges in system design and implementation. To fully utilize the benefits of these new hardware technologies, concurrent design of system, chip, and package is necessary. This research aims to explore the new design space and opportunities for System-on-Package (SoP), with special attention on radio and mixed-signal system applications. Global level system partitioning for SoC and SoP with cost-performance trade-off, concurrent chip and design for high-speed off-chip signaling, global clock distribution, and ultra wideband (UWB) radio module are two fields in this research.

Cost-performance driven for mixed-signal system partitioning in early conceptual level design is first addressed in this thesis. We develop a modeling technique to pre-estimate the cost and performance. The performance model evaluates various noise isolation technologies, such as using guard rings, and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or “virtual components”, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip are considered. An efficient computation algorithm, namely COMSI, is developed for cost estimation under various mixed-signal performance constraints.

System interconnect topologies have been moving away from multi-point bus architecture and towards high-speed serial links. But low interaction between chip and package design has more and more limited system performance. We address concurrent chip and package design and co-optimization for high-speed off-chip signaling in this part. First we explore the interconnect and package constraints to the circuit and system architecture. Proper equivalent circuit models for package parasitics are set up and then a 3-dimension electromagnetic (EM) solver is used to extract the parasitic parameters of package. After that, bandwidth and noise of the signal channel are estimated. The optimal off-chip singling is designed according to these packages and interconnection constraints. We also analyzed the global clock distribution using co-design method.

We developed a low cost, low power consumption, and low complexity UWB radio module using co-design method and SoP technologies. The module will be used in low data rate and long-range wireless intelligent systems such as radio frequency identification (RFID) or wireless sensors networks (WSN). Liquid-crystal-polymer (LCP) based SoP technologies were used to implement the module.

Place, publisher, year, edition, pages
Stockholm: KTH , 2005. , xi, 55 p.
Series
Trita-IMIT. LECS, ISSN 1651-4076 ; 05:09
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-476ISBN: 91-7178-181-7 OAI: oai:DiVA.org:kth-476DiVA: diva2:13809
Public defence
2005-11-24, Sal D, KTH-Forum, Isafjordsgatan 39, Kista, 13:15
Opponent
Supervisors
Note

QC 20101006

Available from: 2005-11-03 Created: 2005-11-03 Last updated: 2012-10-03Bibliographically approved
List of papers
1. Cost and performance analysis for mixed-signal system implementation: system-on-chip or system-on-package?
Open this publication in new window or tab >>Cost and performance analysis for mixed-signal system implementation: system-on-chip or system-on-package?
2002 (English)In: IEEE transactions on electronics packaging manufacturing (Print), ISSN 1521-334X, E-ISSN 1558-0822, Vol. 25, no 4, 262-272 p.Article in journal (Refereed) Published
Abstract [en]

Advances, in integrated circuits and packaging technologies provided us more implementation options for mixed-signal systems. Emerging technologies are represented by system-on-chip (SoC) and system-on-package (SoP). In order to make a design decision or optimal system implementation, it is hence becoming more and more important to address the cost and performance issues for various implementation options early in a system deign phase. In this paper, we develop a modeling technique for a priori cost and performance estimations for mixed-signal system implementations. The performance model evaluates various noise isolation technologies, such as using guard rings, increasing the separation between digital and analog/RF circuitry parts, using special substrate materials (e.g., silicon-on-insulator), and partitioning the system into several chips. Besides, performance of particular analog/RF circuits such as low-noise amplifier (LNA), is also measured by their specific figure-of-merit (FoM), which considered the effects of substrate coupling, the quality factor (Q) of RF components, and packaging parasities. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or "virtual components," yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, are considered. Finally, an efficient computation algorithm, namely COMSI, was developed for cost estimation under various mixed-signal performance constraints. Case studies for SoC and Sol? integration are performed using COMSI.

Keyword
conceptual design, cost analysis, mixed-signal integration, performance estimation, system-on-chip, system-on-package
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-8470 (URN)10.1109/TEPM.2002.807721 (DOI)000180863500005 ()
Note
QC 20101005Available from: 2005-11-03 Created: 2005-11-03 Last updated: 2010-10-05Bibliographically approved
2. Cost and performance tradeoff analysis in radio and mixed-signal system-on-package design
Open this publication in new window or tab >>Cost and performance tradeoff analysis in radio and mixed-signal system-on-package design
Show others...
2004 (English)In: IEEE Transactions on Advanced Packaging, ISSN 1521-3323, E-ISSN 1557-9980, Vol. 27, no 2, 364-375 p.Article in journal (Refereed) Published
Abstract [en]

An optimal total solution for radio and mixed-signal system integration needs tradeoffs between different design options. Among various design metrics, cost and performance are probably the two most important factors for design decisions. In this paper, we review and analyze cost-performance tradeoffs of system-on-chip (SOC) versus system-on-Package (SOP) solutions for radio and mixed-signal applications. A new design methodology, which quantitatively predicts performance and cost gains of SOP versus SOC,is presented. The performance model evaluates various mixed-signal isolation techniques between sensitive analog/RF circuits and noisy digital circuits in SOC or SOP. The cost analysis includes new factors such as extra chip area and additional process steps for mixed-signal isolation, seamless integration of "virtual components" or intellectual property (IP) modules, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, and extra costs for moving passives off chip. In addition to these, a complete and systematic analysis method for on-chip versus off-chip passives tradeoffs is presented. The analysis and modeling techniques explore tradeoffs between performance, cost, robustness, and yield when different on-chip or off-chip passives are used. It thus provides a complete picture of quantitative tradeoffs for using on-chip or off-chip passives. The design methodology and analysis techniques are then demonstrated through several design examples in wireless applications. It is clearly shown that for all complex and high performance mixed-signal systems, SOP is a lower cost solution than SOC. Finally,some design guidelines for SOC versus SOP and on-chip versus off-chip are concluded.

Keyword
cost modelling, mixed-signal systems, performance estimation, radio electronics, system-on-chip (SOC), system-on-package (SOP)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-8471 (URN)10.1109/TADVP.2004.828818 (DOI)000223599100014 ()2-s2.0-4544375231 (Scopus ID)
Note
QC 20100907Available from: 2005-11-03 Created: 2005-11-03 Last updated: 2012-02-14Bibliographically approved
3. Cost-performance driven mixed-signal system partitioning
Open this publication in new window or tab >>Cost-performance driven mixed-signal system partitioning
2004 (English)Conference paper, Published paper (Refereed)
Abstract [en]

For a complex electronic system, early estimation of what technology should be used is very important. In this paper, an optical network access interface is optimally designed according to cost-performance trade-off analysis. The results of the comparison show that for such a complex, mixed-signal system, single chip is not a cost-effective solution compared with single package which has 6 small chips.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-8472 (URN)10.1109/HPD.2004.1346670 (DOI)000224594800009 ()2-s2.0-14844299406 (Scopus ID)0-7803-8620-5 (ISBN)
Conference
Sixth IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, HDP'04, Shanghai, China, 30 June-3 July 2004
Note

QC 20141212

Available from: 2005-11-03 Created: 2005-11-03 Last updated: 2014-12-12Bibliographically approved
4. Robustness enhancement through chip-package co-design for high-speed electronics
Open this publication in new window or tab >>Robustness enhancement through chip-package co-design for high-speed electronics
Show others...
2005 (English)In: Microelectronics Journal, ISSN 0959-8324, Vol. 36, no 9, 846-855 p.Article in journal (Refereed) Published
Abstract [en]

The low interaction between chip and package design has an increasingly limiting effect on the system performance. In this paper, the chip-package co-design flow is presented. We address robustness enhancement under the package and interconnection constraints as well as process, voltage, and temperature (PVT) variations by using impedance control, optimal pins assignment and transmitter equalization. From the simulation results we find that without on-chip digital compensation circuit, the variation of the driver's output impedance is 37% under different PVT conditions. However, it is only 5% when digital compensation circuit is used. Through optimal pins assignment the effective inductance of the pins is reduced. When power and ground pins are used as shielding pins, crosstalk is also decreased by 10 dB. Transmitter equalization effectively decreases inter-symbol interference caused by interconnection attenuation and dispersion. In our design example we find that without equalization the eye-diagram is almost closed at the receiver end. On the other hand with one-tap pre-emphasis equalization the eye-diagram is open and has a height of 90 mV and a width of 140 ps. It is also found that there is a clear optimal window for high data rate in this design. Without a chip-package co-design such an optimal window will not be found.

Keyword
chip-package co-design, pins assignment, impedance-controlled package, equalization
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-8473 (URN)10.1016/j.mejo.2005.03.007 (DOI)000231592000007 ()2-s2.0-23844536828 (Scopus ID)
Note

QC 20100928

Available from: 2005-11-03 Created: 2005-11-03 Last updated: 2012-09-21Bibliographically approved
5. Concurrent chip-package design for 10GHz global clock distribution network
Open this publication in new window or tab >>Concurrent chip-package design for 10GHz global clock distribution network
Show others...
2005 (English)In: 55th Electronic Components & Technology Conference, Vols 1 and 2, 2005 Proceedings, 2005, 1554-1559 p.Conference paper, Published paper (Refereed)
Abstract [en]

As a result of the continuous downscaling of the CMOS technology, on chip frequency for high performance microprocessor will soon arrive 10GHz according to international technology roadmap for semiconductors (ITRS). In this paper, a 10GHz global clock distribution network using standing wave approach was analyzed on chip and package level. On chip level, a 10GHz standing wave oscillator (SWO) for global clock distribution network using 0.18um, 1P6M CMOS technology, is designed and analyzed. The simulation results show that the skew is well controlled (about 1ps) while the clock frequency variation is about 20% because power/ground return paths exist in different metal layers. On package level, we assume that the chip size is 20mm*20mm and flip-chip bonding technology is used. The simulation results show that the skew at random positions of the transmission line (spiral or serpentine shape) is within 10% of tau(clk) when the attenuation is about 1.5dB. For attenuation from 1.5dB to 6.7dB, the peak positions (n*lambda/2) can be used as clock node. For the mesh and plane shape, the skew is controlled within 10% of tau(clk) using standing wave method.

Series
Proceedings - Electronic Components and Technology Conference, ISSN 0569-5503
Keyword
Attenuation, Clocks, CMOS integrated circuits, Concurrent engineering, Microprocessor chips, Semiconductor device manufacture, Transmission line theory
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-8474 (URN)10.1109/ECTC.2005.1441995 (DOI)000230581600243 ()2-s2.0-24644487124 (Scopus ID)0-7803-8906-9 (ISBN)
Conference
Electronic Components and Technology Conference, 2005. Proceedings. 55th, Lake Buena Vista, Florida, USA, May 31- June 3, 2005
Note

QC 20101006

Available from: 2005-11-03 Created: 2005-11-03 Last updated: 2014-12-04Bibliographically approved
6. UWB radio module design for wireless intelligent systems-form specification to implementation
Open this publication in new window or tab >>UWB radio module design for wireless intelligent systems-form specification to implementation
Show others...
2005 (English)Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we designed an impulse-based ultra wideband (UWB) radio module (low band) for wireless intelligent system applications such as radio frequency identification (RFID) and wireless sensor networks (WSN). The UWB radio module includes transceiver block, baseband process unit and power management block. The transceiver circuits include Gaussian pulse generator, wideband low noise amplifier (LNA), multiplier, integrator and timing circuits, which use 0.18mum, 1P6M CMOS technology. The wideband LNA has a power gain of 10dB and minimum noise figure of 2.7dB. For UWB transceiver, the power consumption of transmitter is lower than 1mW while the receiver is about 23mW. The liquid-crystal-polymer (LCP)-based system-on-package (SoP) technology is used to implement the UWB radio module for low power, low cost and small size

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-8475 (URN)10.1109/HDP.2005.251423 (DOI)2-s2.0-42749104860 (Scopus ID)0-7803-9292-2 (ISBN)
Conference
High Density Microsystem Design and Packaging and Component Failure Analysis, 2005
Note

QC 20101006

Available from: 2005-11-03 Created: 2005-11-03 Last updated: 2012-10-02Bibliographically approved

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Permanent link

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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
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  • text
  • asciidoc
  • rtf