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System-on-package solutions for multi-band RF front end
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
2005 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

Advances in microelectronics technology have enabled us to integrate a complex electronic system (such as a radio) on a single chip or in a single package module, known as system-on-chip (SoC) and system-on-package (SoP) paradigms. This brings not only new opportunities for system integration, but also challenges in design and implementation. One of these challenges is how to achieve an optimum total solution of system integration via chip and package co-design, because there is no tool or design methodology available for such kind of optimization. This thesis focuses on innovative multi-band multi-standard radio front-end design and explores a new design methodology. The motivation of developing this design methodology is to achieve an optimum total solution for radio system implementation via chip and package co-design and co-optimization.

The methodology starts from RF packaging and components modeling. Necessary models for both on-chip and off-chip passives are developed. Parasitic effects of packages for radio chips are modeled for particular frequencies. Compared with high-speed digital packaging, RF packaging normally deals with narrow band signals. It is possible to absorb some unwanted parasitics by designing proper port matching networks. In addition, cost-performance trade-offs are performed. In this context, we first developed process and technology based cost models, which include parameters like chip real estate, raw materials, package, test and rework. Impact of process variation on final yield has also been considered in the models by using a statistical analysis approach. Performance of different design options is measured by a special FoM (figure-of-merit). Each type of analog/RF circuit (such as LNA, PA and ADC) has its own dedicated FoM. Through a series of cost-performance trade-offs for different on-chip versus off-chip passives and partitions, an optimum total solution is obtained.

Finally, this methodology was demonstrated via a number of design examples for multi-band multi-standard radio front-end. The author has explored the optimum solutions for different circuit architectures and process technologies encompassing parallel, concurrent and digitally programmable multi-band radio frond-end blocks. It is interesting to find that, for complex RF circuits like a multi-band multi-standard radio, moving some passives off-chip will have significant cost-savings. In addition to the above contributions, the author has also developed an MCM-D technology on LCP and glass substrates, based on metal deposition and BCB spin-coating at KTH clean room. The author has also performed some preliminary studies on UWB radio for RFID applications.

Place, publisher, year, edition, pages
Stockholm: KTH , 2005. , ix, 88 p.
Series
Trita-IMIT. LECS, ISSN 1651-4076 ; 2005:08
Keyword [en]
chip-package co-design, multi-band radio, system-on-package
National Category
Condensed Matter Physics
Identifiers
URN: urn:nbn:se:kth:diva-482ISBN: 91-7178-187-0 (print)OAI: oai:DiVA.org:kth-482DiVA: diva2:14132
Public defence
2005-11-25, Sal D, KTH-Forum, 10:00
Opponent
Supervisors
Note
QC 20101005Available from: 2005-11-09 Created: 2005-11-09 Last updated: 2010-10-05Bibliographically approved
List of papers
1. Modeling and simulation of spiral inductors in wafer level packaged RF/wireless chips
Open this publication in new window or tab >>Modeling and simulation of spiral inductors in wafer level packaged RF/wireless chips
2003 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 34, no 1, 39-47 p.Article in journal (Refereed) Published
Abstract [en]

In this paper, embedded rectangular spiral inductors on Wafer-Level Packaged (WLP) RF/wireless chips were studied with 3D (three-dimensional) EM (electromagnetic) simulations. The performance of spiral inductors fabricated with various geometrical and technological parameters was analyzed. It is shown that Q (the quality factor) and f(res) (the self-resonance frequency) could be improved by using the thick insulator layer and thick/wide metal line, which are fabricated by WLP technology. The value of Q could be over 60 at 20 GHz for such embedded components, attesting a significant improvement compared to the conventional on-chip counterparts in CMOS. Through this study, optimal structures for such components are identified and guidelines for design and fabrications are derived. Finally, a method to estimate the inductance of rectangle spiral inductors is developed. It is useful to determine the approximate structure of an inductor quickly before detailed 3D EM simulation, which may cost a long time.

Place, publisher, year, edition, pages
GZ DORDRECHT: KLUWER ACADEMIC PUBL, 2003
Keyword
silicon
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-22126 (URN)10.1023/A:1020334300576 (DOI)000179895800005 ()
Conference
19th IEEE NORCHIP Conference STOCKHOLM, SWEDEN, NOV 12-13, 2001
Note

QC 20100525

Available from: 2010-08-10 Created: 2010-08-10 Last updated: 2017-12-12Bibliographically approved
2. Cost and performance tradeoff analysis in radio and mixed-signal system-on-package design
Open this publication in new window or tab >>Cost and performance tradeoff analysis in radio and mixed-signal system-on-package design
Show others...
2004 (English)In: IEEE Transactions on Advanced Packaging, ISSN 1521-3323, E-ISSN 1557-9980, Vol. 27, no 2, 364-375 p.Article in journal (Refereed) Published
Abstract [en]

An optimal total solution for radio and mixed-signal system integration needs tradeoffs between different design options. Among various design metrics, cost and performance are probably the two most important factors for design decisions. In this paper, we review and analyze cost-performance tradeoffs of system-on-chip (SOC) versus system-on-Package (SOP) solutions for radio and mixed-signal applications. A new design methodology, which quantitatively predicts performance and cost gains of SOP versus SOC,is presented. The performance model evaluates various mixed-signal isolation techniques between sensitive analog/RF circuits and noisy digital circuits in SOC or SOP. The cost analysis includes new factors such as extra chip area and additional process steps for mixed-signal isolation, seamless integration of "virtual components" or intellectual property (IP) modules, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, and extra costs for moving passives off chip. In addition to these, a complete and systematic analysis method for on-chip versus off-chip passives tradeoffs is presented. The analysis and modeling techniques explore tradeoffs between performance, cost, robustness, and yield when different on-chip or off-chip passives are used. It thus provides a complete picture of quantitative tradeoffs for using on-chip or off-chip passives. The design methodology and analysis techniques are then demonstrated through several design examples in wireless applications. It is clearly shown that for all complex and high performance mixed-signal systems, SOP is a lower cost solution than SOC. Finally,some design guidelines for SOC versus SOP and on-chip versus off-chip are concluded.

Keyword
cost modelling, mixed-signal systems, performance estimation, radio electronics, system-on-chip (SOC), system-on-package (SOP)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-8471 (URN)10.1109/TADVP.2004.828818 (DOI)000223599100014 ()2-s2.0-4544375231 (Scopus ID)
Note
QC 20100907Available from: 2005-11-03 Created: 2005-11-03 Last updated: 2017-12-14Bibliographically approved
3. On-chip versus Off-chip Passives Trade-offs in Radio and Mixed-Signal System-on- Package
Open this publication in new window or tab >>On-chip versus Off-chip Passives Trade-offs in Radio and Mixed-Signal System-on- Package
(English)Manuscript (preprint) (Other academic)
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-24993 (URN)
Note
QC 20101005Available from: 2010-10-05 Created: 2010-10-05 Last updated: 2012-02-14Bibliographically approved
4. On-chip versus off-chip passives in radio and mixed-signal system-on-package design
Open this publication in new window or tab >>On-chip versus off-chip passives in radio and mixed-signal system-on-package design
Show others...
2006 (English)In: ESTC 2006 - 1st Electronics Systemintegration Technology Conference, New York: IEEE , 2006, 221-232 p.Conference paper, Published paper (Refereed)
Abstract [en]

Optimal total solution for new radio architecture and implementation requires accurate trade-offs for off-chip versus off-chip passives. In this paper, a complete and systematic design methodology for RF blocks in SoP (system-on-package) versus SoC (system-on-chip) is presented. This methodology explores trade-offs between Performance and cost when different on-chip or off-chip passives are used. For a better presentation, the method and design techniques are demonstrated through four multi-band/multi-standard radio design examples with various technologies and different circuit topologies. Our study reveals that, in order to obtain cost benefits in RF-SoPs, small RF chips should be merged as larger chips and the integration density of each RF chip should be high enough. Our study also indicates that in a complex chip like a multi-band radio, moving passives off chip could achieve further cost savings and significant performance improvements. These are general conclusions but, our method offers a detailed analysis which can give quantitative measurements of cost savings and performance improvements in off-chip versus off-chip passives in RF SoP design.

Place, publisher, year, edition, pages
New York: IEEE, 2006
Keyword
Bandwidth, Cost effectiveness, Integrated circuit layout, Passive networks, Radio communication
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-25002 (URN)10.1109/ESTC.2006.280002 (DOI)000241425800033 ()2-s2.0-42549084691 (Scopus ID)1-4244-0552-1 (ISBN)978-142440552-7 (ISBN)
Conference
ESTC 2006 - 1st Electronics Systemintegration Technology Conference; Dresden, Saxony; Germany; 5 September 2006 through 7 September 2006
Note

QC 20101005

Available from: 2010-10-05 Created: 2010-10-05 Last updated: 2014-11-26Bibliographically approved
5. Design and implementation of a 5GHz RF receiver front-end in LCP based system-on-package module with embedded chip technology
Open this publication in new window or tab >>Design and implementation of a 5GHz RF receiver front-end in LCP based system-on-package module with embedded chip technology
Show others...
2003 (English)In: ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 2003, 51-54 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we present a receiver front-end for 5 GHz wireless LAN in novel LCP (liquid crystal polymer) based system-on-package module. The module is based on embedded chip technologies for system-on-package, which eliminates the constraints of off-chip pad drive capability and hence improves electrical performance. Furthermore, the novel LCP material shows excellent RF and microwave performance. The quality factors of key passive components such as inductors integrated in LCP substrate with thin film technologies is as high as 60. The insertion loss of the bandpass filter is 3dB. The conversion gain of the receiver front-end is 20 dB and occupies 8.7mm by 3.6mm area.

National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-25004 (URN)10.1109/EPEP.2003.1249998 (DOI)000186891200012 ()0-7803-8128-9 (ISBN)
Conference
12th Topical Meeting on Electrical Performance of Electronic Packaging WESTIN PRINCETON, PRINCETON, NJ, OCT 27-29, 2003
Note
Tidigare titel: Design and Implement of a Receiver Front-End in LCP Based System-on-Package Module with Embedded Chip Technology. QC 20101005Available from: 2010-10-05 Created: 2010-10-05 Last updated: 2010-10-05Bibliographically approved
6. Chip-package co-design of common emitter LNA in system-on-package with on-chip versus off-chip passive component analysis
Open this publication in new window or tab >>Chip-package co-design of common emitter LNA in system-on-package with on-chip versus off-chip passive component analysis
2003 (English)In: ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, NEW YORK: IEEE , 2003, 55-58 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we present common emitter LNAs (low noise amplifiers) in system-on-package for 5GHz WLAN application. Innovation of this module is that it is chip-package co-designed and co-simulated with performance trade-offs for on-chip versus off-chip passive component integration. It thus provides an optimal total solution for embedded RF electronics in system-level integration. Analytical equations for key performance parameters, noise figure and gain, of these LNAs are developed as functions of quality factors of passive components and the package parasitics. They hence provide designers a quantitative trade-off for on-chip versus off-chip passive components integration in SoP design. The final module is composed of on-chip active components in 0.5mum SiGe BiCMOS technology and off-chip passive components integrated in MCM-D substrate. Significant improvement in performance is found in these co-designed LNAs than those in single-chip LNAs.

Place, publisher, year, edition, pages
NEW YORK: IEEE, 2003
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-25008 (URN)10.1109/EPEP.2003.1249999 (DOI)000186891200013 ()
Conference
12th Topical Meeting on Electrical Performance of Electronic Packaging WESTIN PRINCETON, PRINCETON, NJ, OCT 27-29, 2003
Note
QC 20101005Available from: 2010-10-05 Created: 2010-10-05 Last updated: 2010-10-05Bibliographically approved
7. Analysis of lossy packaging parasitics for common emitter LNA in system-on-package
Open this publication in new window or tab >>Analysis of lossy packaging parasitics for common emitter LNA in system-on-package
2004 (English)In: ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, NEW YORK: IEEE , 2004, 75-78 p.Conference paper, Published paper (Refereed)
Abstract [en]

Advances of VLSI and packaging technologies enable condensed integration of an RF system in a single module, known as SoC and SoP. In order to find a better solution between SoC and SoP for RF systems and their sub-systems, it is needed to predict and estimate performance of each solution. In this paper, analytical equations for noise figure and gain of inductively degenerated common-emitter low-noise amplifiers in SoP/SoC are deduced as functions of passives and packaging parasitics. They hence enable designers to evaluate overall performance of each solution quantitatively. As well, influence of lossy packaging parasitics on LNA is also analyzed.

Place, publisher, year, edition, pages
NEW YORK: IEEE, 2004
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-25010 (URN)000225765800018 ()2-s2.0-15944383087 (Scopus ID)0-7803-8667-1 (ISBN)
Conference
13th Topical Meeting on Electrical Performance of Electronic Packaging Portland, OR, OCT 25-27, 2004
Note
QC 20101005Available from: 2010-10-05 Created: 2010-10-05 Last updated: 2012-02-14Bibliographically approved
8. RF robustness enhancement through statistical analysis of chip-package co-design
Open this publication in new window or tab >>RF robustness enhancement through statistical analysis of chip-package co-design
2004 (English)In: 2004 IEEE International Symposium on Cirquits and Systems - Proceedings, IEEE , 2004, 988-991 p.Conference paper, Published paper (Refereed)
Abstract [en]

In order to enhance robustness of RF circuits, a flow of statistical analysis for chip-package co-design of RF system-on-package (SoP) is presented in this work. Methods for improving the yield of RF modules are developed. On-chip passive components versus off-chip passive components trade-offs in SoP module were also analyzed in terms of performance and yield. The design methods were demonstrated through case studies of LNA (low noise amplifier) in SoP.

Place, publisher, year, edition, pages
IEEE, 2004
Series
Proceedings - IEEE International Symposium on Circuits and Systems, ISSN 0271-4310
Keyword
chip scale packaging, integrated circuit yield, multichip modules
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-25013 (URN)10.1109/ISCAS.2004.1328363 (DOI)000223122300248 ()2-s2.0-4344638218 (Scopus ID)0-7803-8251-X (ISBN)
Conference
IEEE International Symposium on Circuits and Systems Vancouver, Canada, May 23-26, 2004
Note

QC 20101005

Available from: 2010-10-05 Created: 2010-10-05 Last updated: 2014-12-09Bibliographically approved
9. A concurrent multi-band LNA for multi-standard radios
Open this publication in new window or tab >>A concurrent multi-band LNA for multi-standard radios
2005 (English)In: 2005 IEEE International Symposium On Circuits And Systems (ISCAS), Conference Proceedings, IEEE , 2005, 3982-3985 p.Conference paper, Published paper (Refereed)
Abstract [en]

A source-degenerated cascade LNA, which works at 2.4GHz and 5.8GHz simultaneously, is designed for Bluetooth and IEEE wireless LAN 802.11 a/b/g receivers. In this design, 0.15 mu m GaAs PHEMT technology and embedded passives in MCM-D substrate are implemented. At 2.4GHz and 5.8GHz, this LNA provides 12.2dB and 15.3dB gain, respectively. Noise figures of the LNA are 0.53dB and 1.43dB, respectively. Good input matching and output matching are also achieved-S11 and S22 at both frequencies are less than -10dB.

Place, publisher, year, edition, pages
IEEE, 2005
Series
IEEE International Symposium on Circuits and Systems, ISSN 0277-674X
Keyword
802.11 a/b/g, Embedded passives, GaAs, Input matching, Multi-standard radio, Multiband, Output matching, pHEMT technology, Wireless LAN
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-25015 (URN)10.1109/ISCAS.2005.1465503 (DOI)000232002403241 ()2-s2.0-35548967599 (Scopus ID)0-7803-8834-8 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS) Kobe, Japan, May 23-26, 2005
Note

QC 20101005

Available from: 2010-10-05 Created: 2010-10-05 Last updated: 2012-10-03Bibliographically approved
10. A study of packaging Requirements Multi-Band/Multi-Standard Wireless Chips
Open this publication in new window or tab >>A study of packaging Requirements Multi-Band/Multi-Standard Wireless Chips
2002 (English)In: Proc. IEEE 20th Norship Conference, 2002, 285-290 p.Conference paper, Published paper (Refereed)
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-25016 (URN)
Conference
IEEE 20th Norship Conference, Copenhagen, Denmark , 2002
Note
QC 20101005Available from: 2010-10-05 Created: 2010-10-05 Last updated: 2010-10-05Bibliographically approved
11. A DC-13GHz LNA for UWB RFID applications
Open this publication in new window or tab >>A DC-13GHz LNA for UWB RFID applications
Show others...
2004 (English)In: 22ND NORCHIP CONFERENCE, PROCEEDINGS, 2004, 241-244 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we present a 4-stage traveling wave lownoise amplifier for UWB RFID (ultra-wideband radiofrequency identification). This LNA covers a frequencyrange of DC - 13 CHz. The circuit is implemented with0.I5pm GaAs PHEMT chips embedded in flexible LCP(liquid crystal polymer) substrate. In the frequency range,the gain of the LNA is better than IO dB, fluctuation of thegain is less than 3dB, its noise figure is less than 4dB, SI 1and S22 are around -10 dB.

National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-25017 (URN)10.1109/NORCHP.2004.1423868 (DOI)000227801500060 ()2-s2.0-21244433177 (Scopus ID)0-7803-8510-1 (ISBN)
Conference
22nd Norchip Conference Location: Oslo, NORWAY Date: NOV 08-09, 2004
Note
QC 20101005Available from: 2010-10-05 Created: 2010-10-05 Last updated: 2012-02-14Bibliographically approved
12. Broadband CMOS LNAs for IR-UWB receiver
Open this publication in new window or tab >>Broadband CMOS LNAs for IR-UWB receiver
2005 (English)In: Norchip 2005, Proceedings, New York: IEEE , 2005, 273-276 p.Conference paper, Published paper (Refereed)
Abstract [en]

Two single-ended wideband LNAs for Ultrawide-band receiver have been designed and implemented in 0.18 mu m CMOS technology. The first one, a feed-back LNA, is a two-stage amplifier with a improved feedback loop, which provides high gain and enables the input port to match with 500 in a wide frequency range from 500MHz to 8GHz. The second one, an LC low-pass-filter matched LNA, employs a third-order low pass filter in the input port to match a frequency range from 3GHz to 8GHz. In both of the LNAs, the input stage is a common source amplifier. Inductive shunt peaking is used for maximizing the bandwidth and flatting the gain. In the feed-back LNA, measurements show that the maximum gain is 11.5dB, the 3-dB; bandwidth is from 500MHz to 7GHz, IIP3 is -2.2dBm at 4GHz, the minimum noise figure is around 5.7dB, S11 is less than 8.2dB, and the power consumption is 14mW. In the LC filter matched LNA, the 3-dB bandwidth is from 3GHz to 7.3GHz. The maximum gain is 9.6dB, IIP3 is 0dBm at 4 GHz, the minimum noise figure is 7.6dB, S11 is less than -13.4dB and the power consumption is 23mW.

Place, publisher, year, edition, pages
New York: IEEE, 2005
Keyword
Bandwidth, CMOS integrated circuits, Gain control, Power amplifiers, Signal receivers, Spurious signal noise
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-25018 (URN)10.1109/NORCHP.2005.1597042 (DOI)000241010100067 ()2-s2.0-33847219622 (Scopus ID)1-4244-0064-3 (ISBN)
Conference
23rd Norchip Conference Oulu, FINLAND, NOV 21-22, 2005
Note

QC 20101005

Available from: 2010-10-05 Created: 2010-10-05 Last updated: 2012-09-26Bibliographically approved

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