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Formal design, co-simulation and validation of a radar signal processing system
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0003-1666-1316
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0003-4859-3100
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2019 (English)In: Proceedings of the 2019 Forum on Specification and Design Languages, FDL 2019, Institute of Electrical and Electronics Engineers Inc. , 2019Conference paper, Published paper (Refereed)
Abstract [en]

With the ever increasing complexity in safety-critical and performance-demanding application domains such as automotive and avionics, the costs of designing, producing and especially testing systems does not scale well for the next generation of applications. One example is the active electronically scanned array (AESA) antenna signal processing chain, which is currently out-of-reach from consumer products but rather part of a few exclusive hi-tech appliances. To cope with the associated complexity of such systems, we propose a design flow starting from a high-level formal modeling language which captures and exposes important design properties to enable their systematic exploitation for the purpose of simulation, analysis and synthesis towards cost-efficient implementations. We demonstrate the capabilities of this approach by providing a compact yet expressive description of the AESA signal processing chain, generate automatic test-cases to verify the conformity of model with design specifications, synthesize a part of it to VHDL and co-simulate the generated artifact to validate its correctness.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc. , 2019.
Keywords [en]
design methodology, model checking, radar, simulation, synthesis, system design language, Antennas, Computer hardware description languages, Computer simulation languages, Consumer products, Cost benefit analysis, Modeling languages, Radar signal processing, Safety engineering, Safety testing, Specifications, Synthesis (chemical), Well testing, Active electronically scanned array, Analysis and synthesis, Design specification, Formal modeling language, System design languages, Testing systems
National Category
Computer Sciences
Identifiers
URN: urn:nbn:se:kth:diva-272362DOI: 10.1109/FDL.2019.8876905Scopus ID: 2-s2.0-85074879329ISBN: 9781728141138 (print)OAI: oai:DiVA.org:kth-272362DiVA, id: diva2:1430110
Conference
2019 Forum for Specification and Design Languages, FDL 2019, Southampton, United Kingdom, September 2-4, 2019
Note

QC 20200513

Available from: 2020-05-13 Created: 2020-05-13 Last updated: 2020-05-13Bibliographically approved

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Ungureanu, GeorgeSander, Ingo

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