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On SiC JFET converters: components, gate-drives and main-circuit conditions
KTH, School of Electrical Engineering (EES), Electrical Machines and Power Electronics (closed 20110930).
2005 (English)Doctoral thesis, monograph (Other scientific)
Abstract [en]

This thesis deals with Silicon Carbide Junction Field Effect Transistors (SiC JFETs) - how to use them to their full potential in power electronic circuits, how to model them in a power electronic simulation program, and how a gate drive can be built.

To fully utilize the low on-state losses of SiC JFETs it is suggested that SiC JFETs should not be equipped with anti-parallel diodes. This is possible due to that JFETs can conduct current in the reverse direction. The circuit making use of this property is called the Diode-less SiC JFET Inverter Bridge (DJIB). The DJIB was studied regarding blanking times, negative voltages, and other special cases.

A gate drive circuit for use with SiC JFETs in industrial applications is presented. The design is with voltage controlled devices(MOSFETs) for use in industrial applications.

Since the JFET model in PSpice had never been validated for SiC power devices, a validation of the PSpice JFET model is presented for SiC JFETs manufactured by SiCED. The PSpice JFET model shows good agreement with measured results up to saturation. For high currents the SiCED SiC JFET saturates much earlier than the PSpice model and this has to be taken into account when making simulations with PSpice.

Due to the high gate-drain capacitance of the SiCED SiC JFETs, there are commutation transients during switching. A short-circuit of the bridge-leg appears due to the high gate-drain capacitance. This is studied and some solutions to this problem are presented.

Simulations on a 1~MW converter utilizing possible future high-voltage SiC JFETs showed that an efficiency of 99,7% could be achieved compared to an efficiency of 98,8% for a converter with Si IGBTs. However, even though the high gate-drain capacitance was reduced in the simulation, undesired commutation transients was observed. This problem has to be considered when designing converters in the future.

Place, publisher, year, edition, pages
2005. , xii, 147 p.
Series
Trita-ETS, ISSN 1650-674X ; 2005-18
Keyword [en]
Power JFET, SiC JFET, Silicon Carbide, PSpice, Simulations, Gate drive, Blanking times, Normally-on, Modeling, Commutation transients
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-558ISBN: 91-7178-230-3 (print)OAI: oai:DiVA.org:kth-558DiVA: diva2:14429
Public defence
2005-12-20, D3, Lindstedtsvägen 5, Stockholm, 10:00
Opponent
Supervisors
Available from: 2005-12-14 Created: 2005-12-14 Last updated: 2012-03-22

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