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Using wormhole switching for networks on chip: feasibility analysis and microarchitecture adaptation
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.ORCID iD: 0000-0003-0061-3475
2005 (English)Licentiate thesis, comprehensive summary (Other scientific)
Abstract [en]

Network-on-Chip (NoC) is proposed as a systematic approach to address future System-on-Chip (SoC) design difficulties. Due to its good performance and small buffering requirement, wormhole switching is being considered as a main network flow control mechanism for on-chip networks. Wormhole switching for NoCs is challenging from NoC application design and switch complexity reduction.

In a NoC design flow, mapping an application onto the network should conduct a feasibility analysis in order to determine whether the messages’ timing constraints can be satisfied, and whether the network can be efficiently utilized. This is necessary because network contentions lead to nondeterministic behavior in message delivery. For wormhole-switched networks, we have formulated a contention tree model to accurately capture network contentions and reflect the concurrent use of links. Based on this model, the timing bounds of real-time messages can be derived. Furthermore, we have developed an algorithm to test the feasibility of real-time messages in the networks.

From the wormhole switch micro-architecture level, switch complexity should be minimized to reduce cost but with reasonable performance penalty. We have investigated the flit admission and flit ejection problems that concern how the flits of packets are admitted into and ejected from the network, respectively. For flit admission, we propose a novel coupling scheme which binds a flit-admission queue with an output physical channel. Our results show that this scheme achieves a reduction of up to 8% in switch area and up to 35% in switch power over other comparable solutions. For flit ejection, we propose a p-sink model which differs from a typical ideal ejection model in that it uses only p flit sinks to eject flits instead of p • v flit sinks as required by the ideal model, where p is the number of physical channels of a switch and v is the number of virtual channels per physical channel. With this model, the buffering cost of flit sinks only depends on p, i.e., is irrespective of v. We have evaluated the coupled flit-admission technique and p-sink model in a 2D 4 x 4 mesh network. In our experiments, they exhibit only limited performance penalties in some cases. We believe that these cost-effective models are promising candidates to be used in wormhole-switched on-chip networks.

Place, publisher, year, edition, pages
Stockholm: KTH , 2005. , x, 46 p.
Series
Trita-IMIT. LECS, ISSN 1651-4076 ; 2005:5
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-562OAI: oai:DiVA.org:kth-562DiVA: diva2:14439
Presentation
(English)
Note
QC 20100524Available from: 2005-12-28 Created: 2005-12-28 Last updated: 2012-03-23Bibliographically approved
List of papers
1. Feasibility analysis of messages for on-chip networks using wormhole routing
Open this publication in new window or tab >>Feasibility analysis of messages for on-chip networks using wormhole routing
2005 (English)In: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, IEEE conference proceedings, 2005, 960-964 p.Conference paper, Published paper (Refereed)
Abstract [en]

The feasibility of a message in a network concerns if its timing property can be satisfied without jeopardizing any messages already in the network to meet their timing properties. We present a novel feasibility analysis for real-time (RT) and non-realtime (NT) messages in wormhole-routed networks on chip. For RT messages, we formulate a contention tree that captures contentions in the network. For coexisting RT and NT messages, we propose a simple bandwidth partitioning method that allows us to analyze their feasibility independently.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2005
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-13035 (URN)000245021700193 ()2-s2.0-70349787717 (Scopus ID)
Conference
10th Asia and South Pacific Design Automation Conference. Shanghai, PEOPLES R CHINA. JAN 18-21, 2005
Note

QC 20100525. QC 20160212

Available from: 2010-05-25 Created: 2010-05-24 Last updated: 2016-02-12Bibliographically approved
2. Flit admission in on-chip wormhole-switched networks with virtual channels
Open this publication in new window or tab >>Flit admission in on-chip wormhole-switched networks with virtual channels
2004 (English)In: 2004 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS, IEEE conference proceedings, 2004, 21-24 p.Conference paper, Published paper (Refereed)
Abstract [en]

Flit-admission solutions for wormhole switches must minimize the complexity of the switches in order to achieve cheap implementations. We propose to couple flit-admission buffers with physical channels so that flits from a flit-admission buffer are dedicated to a physical channel. By the coupling strategy, for input-queuing wormhole lane switches, the complexity of the crossbars can be simplified from 2p x p to (p + 1) x p, where p is the number of physical channels; for output-queuing wormhole lane switches, the additional complexity is also minimal. We evaluate the flit-admission solutions derived from the coupling with uniformly distributed random traffic in a 2D mesh network. Experimental results show that these solutions exhibit good performance in terms of latency and throughput.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2004
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-13036 (URN)000227185900005 ()2-s2.0-21244466371 (Scopus ID)
Conference
International Symposium on System-on-Chip, Tampere, Finland, November 2004.
Note

QC 20100524. QC 20160212

Available from: 2010-05-24 Created: 2010-05-24 Last updated: 2016-02-12Bibliographically approved
3. Flit ejection in on-chip wormhole-switched networks with virtual channels
Open this publication in new window or tab >>Flit ejection in on-chip wormhole-switched networks with virtual channels
2004 (English)In: 22ND NORCHIP CONFERENCE, PROCEEDINGS, IEEE conference proceedings, 2004, 273-276 p.Conference paper, Published paper (Refereed)
Abstract [en]

An ideal it-ejection model is typically assumed in the literature for wormhole switches with virtual channels. With such a model, its are ejected from the network immediately upon reaching their destinations. This achieves optimal performance but is very costly. The required number of sink queues of a switch for absorbing its is p center dot v, where p is the number of physical channels (PCs) of the switch; v the number of lanes per PC To achieve cheap silicon implementations, it-ejection solutions must be cost-effective. We present a novel it-ejection model and a variant of it where the required number of sink queues of a switch is p, i.e., independent of v. We evaluate the it-ejection models with uniformly distributed random traf c in a 2D mesh network. Experimental results show that they exhibit good performance in latency and throughput.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2004
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-13037 (URN)10.1109/NORCHP.2004.1423876 (DOI)000227801500068 ()2-s2.0-21244435987 (Scopus ID)
Conference
IEEE NorChip Conference, Oslo, Norway, November 2004.
Note

QC 20100524. QC 20160212

Available from: 2010-05-24 Created: 2010-05-24 Last updated: 2016-02-12Bibliographically approved
4. A power efficient flit-admission scheme for wormhole-switched networks on chip
Open this publication in new window or tab >>A power efficient flit-admission scheme for wormhole-switched networks on chip
2005 (English)In: WMSCI 2005: 9th World Multi-Conference on Systemics, Cybernetics and Informatics, Vol 4 / [ed] Callaos, N; Lesso, W; Palesi, M, 2005, 25-30 p.Conference paper, Published paper (Refereed)
Abstract [en]

Reducing power consumption is a main challenge when adopting a network as a global on-chip communication interconnect since the reduction in power dissipation should not at the expense of degrading the system performance. We investigate power in a wormhole-switched network with focus on the impact of flit-admission schemes, i.e., when and how the flits of packets are admitted into the network We have proposed a novel flit-admission scheme that shows significant shrink of the switch complexity while maintaining equivalent network performance. This paper investigates its influence in network power involving both switches and links. We conduct experiments on a 2D mesh network. The results show that our flit-admission scheme achieves significant power and area reduction without performance penalty. To our knowledge, our work is the first study of power dissipation on flit admission schemes.

Keyword
power consumption, network-on-chip
National Category
Computer and Information Science
Identifiers
urn:nbn:se:kth:diva-43345 (URN)000243684900005 ()2-s2.0-84867373574 (Scopus ID)978-980-6560-56-7 (ISBN)
Conference
9th World Multi-Conference on Systemics, Cybernetics and Informatics Location: Orlando, FL Date: JUL 10-13, 2005
Note

QC 20111014

Available from: 2011-10-14 Created: 2011-10-14 Last updated: 2012-09-21Bibliographically approved
5. NNSE: Nostrum Network-on-Chip Simulation Environment
Open this publication in new window or tab >>NNSE: Nostrum Network-on-Chip Simulation Environment
Show others...
2005 (English)In: Proceedings of Swedish System-on-Chip Conference, Stockholm, Sweden, April 2005., 2005Conference paper, Published paper (Other academic)
Abstract [en]

A main challenge for Network-on-Chip (NoC) design isto select a network architecture that suits a particular application.NNSE enables to analyze the performance impactof NoC configuration parameters. It allows one to(1) configure a network with respect to topology, flow controland routing algorithm etc.; (2) configure various regularand application specific traffic patterns; (3) evaluatethe network with the traffic patterns in terms of latency and throughput.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-13033 (URN)
Conference
Swedish System-on-Chip Conference
Note

QC 20100524

Available from: 2010-05-24 Created: 2010-05-24 Last updated: 2012-09-21Bibliographically approved
6. Traffic configuration for evaluating networks on chips
Open this publication in new window or tab >>Traffic configuration for evaluating networks on chips
2005 (English)In: Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings, IEEE Computer Society, 2005, 535-540 p.Conference paper, Published paper (Refereed)
Abstract [en]

Network-on-Chip (NoC) provides a network as a global communication platform for future SoC designs. Evaluating network architectures requires both synthetic workloads and application-oriented traffic. We present our traffic configuration methods that can be used to configure uniform and locality traffic as synthetic workloads, and to configure channel-based traffic for specific application(s). We also illustrate the significance of applying these methods to configure traffic for network evaluation and system simulation. These traffic configuration methods have been integrated into our Nostrum NoC simulation environment.

Place, publisher, year, edition, pages
IEEE Computer Society, 2005
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-13038 (URN)000231591800102 ()2-s2.0-33748913346 (Scopus ID)0-7695-2403-6 (ISBN)
Conference
5th International Workshop on System-on- Chip for Real-time Applications, Alberta, Canada, July 2005
Note

QC 20100524. QC 20160209

Available from: 2010-05-24 Created: 2010-05-24 Last updated: 2016-02-09Bibliographically approved

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