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MOSFETs with recessed SiGe Source/Drain junctions formed by selective etching and growth
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.ORCID iD: 0000-0001-6705-1660
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
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2004 (English)In: Electrochemical and solid-state letters, ISSN 1099-0062, E-ISSN 1944-8775, Vol. 7, no 4, G53-G55 p.Article in journal (Refereed) Published
Abstract [en]

A source/drain extension process that uses HCl etching followed by selective growth of in situ B-doped SiGe is demonstrated. The two key process steps, etching and growth, are integrated by performing them consecutively in the same chemical vapor deposition reactor. The technique has the potential to solve end-of-the-roadmap requirements on junction depth, junction abruptness, and active doping concentration.

Place, publisher, year, edition, pages
2004. Vol. 7, no 4, G53-G55 p.
Keyword [en]
Chemical vapor deposition, Concentration (process), Electric conductivity, Etching, Evaporation, Polycrystalline materials, Secondary ion mass spectrometry, Semiconducting silicon compounds, Semiconductor growth, Semiconductor junctions, Transmission electron microscopy
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-9102DOI: 10.1149/1.1646833ISI: 000189265100015Scopus ID: 2-s2.0-1842582455OAI: oai:DiVA.org:kth-9102DiVA: diva2:14958
Note
QC 20100923Available from: 2005-02-02 Created: 2005-02-02 Last updated: 2017-12-14Bibliographically approved
In thesis
1. Source and drain engineering in SiGe-based pMOS transistors
Open this publication in new window or tab >>Source and drain engineering in SiGe-based pMOS transistors
2005 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

A new shallow junction formation process, based on selective silicon etching followed by selective growth of in situ B-doped SiGe, is presented. The approach is advantageous compared to conventional ion implantation followed by thermal activation, because perfectly abrupt, low resistivity junctions of arbitrary depth can be obtained. In B-doped SiGe layers, the active doping concentration can exceed the solid solubility in silicon because of strain compensation. In addition, the compressive strain induced in the Si channel can improve drivability through increased hole mobility. The process is integrated by performing the selective etching and the selective SiGe growth in the same reactor. The main advantage of this is that the delicate gate oxide is preserved. The silicon etching process (based on HCl) is shown to be highly selective over SiO2 and anisotropic, exhibiting the densely packed (100), (311) and (111) surfaces. It was found that the process temperature should be confined between 800 ºC, where etch pits occur, and 1000 ºC, where the masking oxide is attacked. B-doped SiGe layers with a resistivity of 5×10-4 Ωcm were obtained. Well-behaved pMOS transistors are presented, yet with low layer quality. Therefore integration issues related to the epitaxial growth, such as selectivity, loading effect, pile-up and defect generation, were investigated. Surface damage originating from reactive-ion etching of the sidewall spacer and nitride residues from LOCOS formation were found to degrade the quality of the SiGe layer. Various remedies are discussed. Nevertheless, high-quality selective epitaxial growth could not be achieved with a doping concentration in the 1021 cm-3 range. The maximum doping level resulting in a high-quality layer, with the loading effect taken into account, was 6×1020 cm-3. After this careful process optimization, a high-quality layer was obtained in the recessed areas. Finally, Ni mono-germanosilicide was investigated as a material for contact formation to the epitaxial SiGe layers in the recessed source and drain areas. The formation temperature is 550 ºC and it is stable up to 700 ºC. The observation of a recessed step and lateral growth of the silicide led to a detailed treatment of the contact resistivity of the NiSi0.8Ge0.2/Si0.8Ge0.2 interface using 2-D as well as 3-D modeling. Different values were obtained for square shaped and rounded contacts, 5.0x10-8 Ωcm2 and 1.4x10-7 Ωcm2, respectively.

Place, publisher, year, edition, pages
Stockholm: KTH, 2005. xii, 54 p.
Series
Trita-EKT, ISSN 1650-8599 ; 2005:1
Keyword
Electronics, SiGe, source/drain, shallow junctions, pMOS, process integration, CVD, epitaxy, etching, Ni silicide, contact resistivity, Elektronik
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-96 (URN)
Public defence
2005-01-14, C1, Electrum, Isafjordsgatan 22, Kista, 10:15
Opponent
Supervisors
Note
QC 20101028Available from: 2005-02-02 Created: 2005-02-02 Last updated: 2010-10-28Bibliographically approved

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Hellström, Per-Erik

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