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Source and drain engineering in SiGe-based pMOS transistors
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
2005 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

A new shallow junction formation process, based on selective silicon etching followed by selective growth of in situ B-doped SiGe, is presented. The approach is advantageous compared to conventional ion implantation followed by thermal activation, because perfectly abrupt, low resistivity junctions of arbitrary depth can be obtained. In B-doped SiGe layers, the active doping concentration can exceed the solid solubility in silicon because of strain compensation. In addition, the compressive strain induced in the Si channel can improve drivability through increased hole mobility. The process is integrated by performing the selective etching and the selective SiGe growth in the same reactor. The main advantage of this is that the delicate gate oxide is preserved. The silicon etching process (based on HCl) is shown to be highly selective over SiO2 and anisotropic, exhibiting the densely packed (100), (311) and (111) surfaces. It was found that the process temperature should be confined between 800 ºC, where etch pits occur, and 1000 ºC, where the masking oxide is attacked. B-doped SiGe layers with a resistivity of 5×10-4 Ωcm were obtained. Well-behaved pMOS transistors are presented, yet with low layer quality. Therefore integration issues related to the epitaxial growth, such as selectivity, loading effect, pile-up and defect generation, were investigated. Surface damage originating from reactive-ion etching of the sidewall spacer and nitride residues from LOCOS formation were found to degrade the quality of the SiGe layer. Various remedies are discussed. Nevertheless, high-quality selective epitaxial growth could not be achieved with a doping concentration in the 1021 cm-3 range. The maximum doping level resulting in a high-quality layer, with the loading effect taken into account, was 6×1020 cm-3. After this careful process optimization, a high-quality layer was obtained in the recessed areas. Finally, Ni mono-germanosilicide was investigated as a material for contact formation to the epitaxial SiGe layers in the recessed source and drain areas. The formation temperature is 550 ºC and it is stable up to 700 ºC. The observation of a recessed step and lateral growth of the silicide led to a detailed treatment of the contact resistivity of the NiSi0.8Ge0.2/Si0.8Ge0.2 interface using 2-D as well as 3-D modeling. Different values were obtained for square shaped and rounded contacts, 5.0x10-8 Ωcm2 and 1.4x10-7 Ωcm2, respectively.

Place, publisher, year, edition, pages
Stockholm: KTH , 2005. , xii, 54 p.
Series
Trita-EKT, ISSN 1650-8599 ; 2005:1
Keyword [en]
Electronics, SiGe, source/drain, shallow junctions, pMOS, process integration, CVD, epitaxy, etching, Ni silicide, contact resistivity
Keyword [sv]
Elektronik
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-96OAI: oai:DiVA.org:kth-96DiVA: diva2:14962
Public defence
2005-01-14, C1, Electrum, Isafjordsgatan 22, Kista, 10:15
Opponent
Supervisors
Note
QC 20101028Available from: 2005-02-02 Created: 2005-02-02 Last updated: 2010-10-28Bibliographically approved
List of papers
1. Selective Si etching using HCl vapor
Open this publication in new window or tab >>Selective Si etching using HCl vapor
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2004 (English)In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T114, 107-109 p.Article in journal (Refereed) Published
Abstract [en]

Selective Si etching using HCl in a reduced pressure chemical vapor deposition reactor in the temperature range 800-1000 degrees C is investigated. At 900 degrees C, the etch process is anisotropic, exhibiting the densely packed (100), (311) and (111) surfaces. This behavior indicates that the etch process is limited by surface reaction, since the etch rate in the directions with higher atomic concentration is lower. When the temperature is decreased to 800 degrees C, etch pits occur. A more isotropic etch is obtained at 1000 degrees C, however at this temperature the masking oxide is attacked and the etch surface is rough. Thus the temperature has to be confined to a narrow window to yield desirable properties under the present process conditions.

Keyword
Anisotropic etching, Chemical vapor deposition, Hydrochloric acid, Surface reactions, Atomic concentration, Masking oxide
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-9099 (URN)10.1088/0031-8949/2004/T114/026 (DOI)000204272000027 ()2-s2.0-34247183792 (Scopus ID)
Note
QC 20101027. Uppdaterad från in press till published (20101027).Available from: 2005-02-02 Created: 2005-02-02 Last updated: 2010-10-27Bibliographically approved
2. Formation of shallow junctions by HCl-based Si etch followed by selective epitaxy of B-doped Si1-xGex in RPCVD
Open this publication in new window or tab >>Formation of shallow junctions by HCl-based Si etch followed by selective epitaxy of B-doped Si1-xGex in RPCVD
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2004 (English)In: Journal of the Electrochemical Society, ISSN 0013-4651, Vol. 151, no 6, C365-C368 p.Article in journal (Refereed) Published
Abstract [en]

Formation of shallow source/drain junctions by using HCl-based Si etch followed by selective deposition of in situ heavily B-doped SiGe in a reduced pressure chemical vapor deposition reactor is presented. The etching parameters were optimized to obtain a smooth surface prior to deposition of the SiGe layers. In the epitaxy process, SiGe layers with a resistivity of 5 x 10(-4) Omega cm were obtained by tuning the partial pressure of the B and Ge precursors. A problem with selectivity in the epitaxy step was encountered when combing the etch and growth processes, but a practical solution is presented. Integration issues such as loading effect, pile-up, and defect generation have also been investigated.

Keyword
gas-phase, silicon, growth, layers, films
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-23417 (URN)10.1149/1.1737387 (DOI)000221437300035 ()2-s2.0-2942668441 (Scopus ID)
Note
QC 20100525Available from: 2010-08-10 Created: 2010-08-10 Last updated: 2010-10-27Bibliographically approved
3. Process integration of a new method for formation of shallow junctions in MOSFET structures using recessed and selectively regrown Si1-xGex
Open this publication in new window or tab >>Process integration of a new method for formation of shallow junctions in MOSFET structures using recessed and selectively regrown Si1-xGex
2004 (English)Conference paper, Published paper (Refereed)
Abstract [en]

Process integration issues concerning recessed epitaxial SiGe(B) source/drain junctions formed by selective Si etching followed by selective epitaxial growth of in situ heavily B-doped Si1-xGex are presented. The proposed concept is beneficial compared to conventional ion implanted junctions, since dopant activation above the solid solubility in Si can be obtained. Nitride residues and surface damage originating from RIE are shown to be detrimental for the epitaxial quality.

Keyword
Chemical vapor deposition, Etching, Nitrides, Semiconducting silicon compounds, Semiconductor doping, Semiconductor growth, Semiconductor junctions, Silicon compounds, Solubility, Strain, Short-channel effect (SCE), Solid solubility, Source/Drain extension (SDE), Strain compensation effect
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-9101 (URN)2-s2.0-17044383842 (Scopus ID)
Conference
SiGe: Materials, Processing, and Devices - Proceedings of the First Symposium; Honolulu, HI; United States; 3 October 2004 through 8 October 2004
Note

QC 20101027

Available from: 2005-02-02 Created: 2005-02-02 Last updated: 2014-12-09Bibliographically approved
4. MOSFETs with recessed SiGe Source/Drain junctions formed by selective etching and growth
Open this publication in new window or tab >>MOSFETs with recessed SiGe Source/Drain junctions formed by selective etching and growth
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2004 (English)In: Electrochemical and solid-state letters, ISSN 1099-0062, Vol. 7, no 4, G53-G55 p.Article in journal (Refereed) Published
Abstract [en]

A source/drain extension process that uses HCl etching followed by selective growth of in situ B-doped SiGe is demonstrated. The two key process steps, etching and growth, are integrated by performing them consecutively in the same chemical vapor deposition reactor. The technique has the potential to solve end-of-the-roadmap requirements on junction depth, junction abruptness, and active doping concentration.

Keyword
Chemical vapor deposition, Concentration (process), Electric conductivity, Etching, Evaporation, Polycrystalline materials, Secondary ion mass spectrometry, Semiconducting silicon compounds, Semiconductor growth, Semiconductor junctions, Transmission electron microscopy
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-9102 (URN)10.1149/1.1646833 (DOI)000189265100015 ()2-s2.0-1842582455 (Scopus ID)
Note
QC 20100923Available from: 2005-02-02 Created: 2005-02-02 Last updated: 2011-10-31Bibliographically approved
5. pMOSFETs with recessed and selectively regrown Si1-xGex source/drain junctions
Open this publication in new window or tab >>pMOSFETs with recessed and selectively regrown Si1-xGex source/drain junctions
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2005 (English)In: Materials Science in Semiconductor Processing, ISSN 1369-8001, Vol. 8, no 1-3, 359-362 p.Article in journal (Refereed) Published
Abstract [en]

A new source/drain formation concept based on selective Si etching followed by selective regrowth of in situ B-doped Si(1-x)Ge(x)is presented. Both process steps are performed in the same reactor to preserve the gate oxide. Well-behaved transistors are demonstrated with a negligibly low gate-to-substrate leakage current.

Keyword
pMOS, shallow junctions, CVD, Si1-xGex
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-9103 (URN)10.1016/j.mssp.2004.09.045 (DOI)000227056200065 ()2-s2.0-13244272291 (Scopus ID)
Note
QC 20101027. Uppdaterad från in press till published (20101027).Available from: 2005-02-02 Created: 2005-02-02 Last updated: 2011-10-12Bibliographically approved
6. Formation of Ni mono-germanosilicide on heavily B-doped epitaxial SiGe for ultra-shallow source/drain contacts
Open this publication in new window or tab >>Formation of Ni mono-germanosilicide on heavily B-doped epitaxial SiGe for ultra-shallow source/drain contacts
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2003 (English)In: Materials Research Society Symposium Proceedings, ISSN 0272-9172, Vol. 745, 117-122 p.Article in journal (Refereed) Published
Abstract [en]

The formation of Ni germanosilicides during solid-state interaction between Ni and heavily B-doped strained epitaxial Si1-xGex films with x=0.18, 0.32 and 0.37 is studied. No NiSi2 is found in these samples even after annealing at 850 degreesC, which can be compared to the formation of NiSi2 at 750 T on Si(I 00). Resistance and diffraction studies for the Si0.82Ge0.18 sample indicate that NiSi0.82Ge0.18 forms and the NiSi0.82Ge0.18/Si0.82Ge0.18 structure is stable from 400 to 700 degreesC. For the NiSi1-uGeu formed in all Si1-xGex samples, where u can be different from x, a strong film texturing is observed. When the Ge fraction is increased from 18 at.% to 32-37 at.%, the morphological stability of the film is degraded and a substantial increase in sheet resistance occurs already at 600 degreesC. The contact resistivity for the NiSi0.8Ge0.2/Si0.8Ge0.2 interface formed at 550 T is determined as 1.2x10(-7) Omegacm(2), which satisfies the ITRS contact resistivity requirement for the 70 nm technology node.

Keyword
Electric contacts, Electric resistance, Epitaxial growth, Rapid thermal annealing, Semiconducting films, Semiconductor doping, Semiconductor junctions, X ray diffraction analysis, Sheet resistance, Silicidation
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-9104 (URN)000182316500018 ()
Note
QC 20101027Available from: 2005-02-02 Created: 2005-02-02 Last updated: 2010-10-28Bibliographically approved
7. Lateral growth and three-dimensional effects in contacts between NiSi0.82Ge0.18 and p(+)-Si0.82Ge0.18
Open this publication in new window or tab >>Lateral growth and three-dimensional effects in contacts between NiSi0.82Ge0.18 and p(+)-Si0.82Ge0.18
2005 (English)In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 489, no 1-2, 159-163 p.Article in journal (Refereed) Published
Abstract [en]

Electrical contacts of NiSi0.82Ge0.18 to P+-Si0.82Ge0.18 were fabricated and characterised. Lateral growth of the NiSi0.82Ge0.18 under SiO2 isolation was observed. A three-dimensional model was employed to extract the contact resistivity by considering both the lateral growth and the presence of a recessed NiSi0.82Ge0.18 step into the Si0.82Ge0.18. The contact resistivity extracted was 5.0 x 10(-8) and 1.4 x 10(-7) Omega cm(2) for small contacts of circular geometry and large contacts of square shape, respectively. Possible causes responsible for this 3-fold difference in contact resistivity were discussed. An underestimate of the contact resistivity by 35% was found if a two-dimensional model was used without taking into account the complex interface morphology.

Keyword
nickel silicides, silicon-germanium, contacts, interfaces
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-9105 (URN)10.1016/j.tsf.2005.04.090 (DOI)000231435400025 ()2-s2.0-23144447233 (Scopus ID)
Note
QC 20101028. Uppdaterad från accepted till published (20101028).Available from: 2005-02-02 Created: 2005-02-02 Last updated: 2010-10-28Bibliographically approved

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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
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  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
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Output format
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