Hierarchical Fault Simulation of Deep Neural Networks on Multi-Core SystemsShow others and affiliations
2021 (English)In: 2021 IEEE EUROPEAN TEST SYMPOSIUM (ETS 2021), Institute of Electrical and Electronics Engineers (IEEE) , 2021Conference paper, Published paper (Refereed)
Abstract [en]
In this paper, a hierarchical fault simulation technique for neural networks is proposed, supporting both permanent and temporary faults. In the proposed technique, different levels of hierarchy are used, forming a mixed-level simulation environment. In such an environment, the pre-synthesis behavioral specification of the network and the post-synthesis gate-level model are co-simulated. To accelerate the fault simulation process, faults are injected in the gate-level specification of the selected neurons while the behavioral model in different levels of abstraction is used to simulate the remaining neurons. Further speedup is obtained through event-driven simulation and parallelization. Experimental results confirm the time efficiency of the proposed fault simulation technique.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2021.
Series
Proceedings of the European Test Symposium, ISSN 1530-1877
Keywords [en]
Fault Simulation, Neural Network, Reliability
National Category
Computer and Information Sciences
Identifiers
URN: urn:nbn:se:kth:diva-302599DOI: 10.1109/ETS50041.2021.9465432ISI: 000693413600023Scopus ID: 2-s2.0-85113716721OAI: oai:DiVA.org:kth-302599DiVA, id: diva2:1606538
Conference
26th IEEE European Test Symposium (ETS),[Online], May 24-28, 2021.
Note
Part of proceedings: ISBN 978-1-6654-1849-2, QC 20230117
2021-10-272021-10-272023-01-17Bibliographically approved