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The Impact of Faults on DNNs: A Case Study
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0002-6100-6305
Inst Res Fundamental Sci IPM, Sch Comp Sci, Tehran, Iran..
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0003-0061-3475
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0001-7877-6712
2021 (English)In: 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) / [ed] Dilillo, L Cassano, L Papadimitriou, A, Institute of Electrical and Electronics Engineers (IEEE) , 2021Conference paper, Published paper (Refereed)
Abstract [en]

Deep neural networks (DNNs) are showing superior advantages in different domains and are opening their path into critical applications where reliability is the main concern. DNNs can be executed in different hardware platforms, including general-purpose processors which usually operate under floating-point (FP) numbering systems. Considering the small range of weights in DNNs stored in the FP format, some bits remain constant as 0 or 1 for all weights. On the other hand, a single event upset may flip a bit, increasing or decreasing the value of a weight. In this paper, we analyze the effect of bit flips in a sample network of LeNet5, and show the sensitivity of convolution layers to faults and the vulnerability of DNNs to a single fault in a specific bit position. This is while the network is inherently robust against bit flips in the other bit positions. We then show that the choice of activation functions and pooling techniques could alleviate the negative effects of faults to a large extend.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2021.
Series
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, ISSN 1550-5774
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-310277DOI: 10.1109/DFT52944.2021.9568340ISI: 000758751600023Scopus ID: 2-s2.0-85142889772OAI: oai:DiVA.org:kth-310277DiVA, id: diva2:1647715
Conference
34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), OCT 06-08, 2021, ELECTR NETWORK
Note

QC 20220328

Part of proceedings: ISBN 978-1-6654-1609-2

Available from: 2022-03-28 Created: 2022-03-28 Last updated: 2023-11-29Bibliographically approved

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Malekzadeh, ElahehLu, ZhonghaiEbrahimi, Masoumeh

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