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Flexible and Efficient QoS Provisioning in AXI4-based Network-on-Chip Architecture
Beijing Institute of Biotechnology, 100 071 Beijing, China.
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0003-0061-3475
2022 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 41, no 5, p. 1523-1536Article in journal (Refereed) Published
Abstract [en]

We propose a Network-on-Chip (NoC)-based whole system design, whose communication architecture is compatible with the AMBA AXI4 protocol and supports high-performance multiple Quality-of-Service (QoS) schemes. In our system, the network interface (NI) between the NoC and the master/slave node is proposed to make the NoC architecture independent from the AXI4 protocol via message format conversion between the AXI4 signal format and the packet format, offering high flexibility to the NoC design. Besides, a QoS inheritance mechanism is applied in the slave-side NI to support QoS during packets’ round-trip transfer in the NoC. The NoC system contains Time Division Multiplexing (TDM) and Virtual Channel (VC) subnetworks to apply multiple QoS schemes to AXI4 signals with different QoS tags and the NI is responsible for signals distribution between two subnetworks. Besides, a traffic converter is proposed in each NI to balance the traffic between the two subnetworks when necessary. The experimental results show that our proposed architecture ensures a high-throughput and low-latency NoC system. By applying traffic converter, the packet latency can be improved. CCBY

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2022. Vol. 41, no 5, p. 1523-1536
Keywords [en]
Computer architecture, Integrated circuit interconnections, Protocols, Quality of service, Regulation, Routing, Time division multiplexing, Internet protocols, Network architecture, Network-on-chip, Servers, Communication architectures, Inheritance mechanisms, Multiple quality, Network-on-chip architectures, Network-on-chip(NoC), NoC architectures, Packet latencies, Proposed architectures, Integrated circuit design
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:kth:diva-311087DOI: 10.1109/TCAD.2021.3091410ISI: 000784196800029Scopus ID: 2-s2.0-85112418084OAI: oai:DiVA.org:kth-311087DiVA, id: diva2:1652440
Note

QC 20220509

Available from: 2022-04-19 Created: 2022-04-19 Last updated: 2022-06-25Bibliographically approved

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Lu, Zhonghai

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